Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs

IEEE Transactions on Electron Devices

Volumn 53, Issue 5, 2006, Pages 979-989

  Song, Seung Chul ^a   Zhang, Zhibo ^b   Huffman, Craig ^b   Sim, Jang H ^a   Bae, Sang Ho ^a   Kirsch, Paul D ^c   Majhi, Prashant ^d   Choi, Rino ^a   Moumen, Naim ^c   Lee, Byoung Hun ^c  

^a SEMATECH   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c IBM   (United States)

^d INTEL CORPORATION   (United States)

Author keywords

Boron diffusion; Charge trapping; CMOSFET; Dual metal gate; Electron mobility; Equivalent oxide thickness (EOT); Gate first; Hafnium; Hf silicate; HfO2; High ; Metal gate; NH3; TiN

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRODES; ELECTRON MOBILITY; ELECTRON TRAPS; GATES (TRANSISTOR); OPTIMIZATION; STRESSES;

BORON DIFFUSION; CHARGE TRAPPING; DOPANT DIFFUSION; DUAL METAL GATE; EQUIVALENT OXIDE THICKNESS (EOT); GATE-STACK PROCESS; METAL ELECTRODE; PHYSICAL-STRESS EFFECTS;

MOSFET DEVICES;

EID: 33646057281     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.872700     Document Type: Article

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