Fringing-induced barrier lowering (FIBL) in sub-100nm MOSFETs with high-K gate dielectrics

Electronics Letters

Volumn 34, Issue 11, 1998, Pages 1150-1152

  Yeap, G C F ^a   Krishnan, S ^a   Lin, Ming Ren ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC DEVICES; GATES (TRANSISTOR);

FRINGING INDUCED BARRIER LOWERING (FIBL);

MOSFET DEVICES;

EID: 0032072440     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19980800     Document Type: Article

References (3)

1. 'National technology roadmap for semiconductors' 1997 edition, Semiconductor Industry Association, San Jose, CA, USA
2. BUCHANAN, D.A., and LO, S.H.: 'Reliability and integration of ultrathin gate dielectrics for advanced CMOS', Microelectron. Eng., 1997, 36, pp. 13-20
3. MEDICI User's Manual, Version 4.0, October 1997, Technology Modeling Associates, Sunnyvale, CA, USA