Integration issues of high-k gate stack: Process-induced charging

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 479-484

  Bersuker, G ^a   Gutt, J ^a   Chaudhary, N ^a   Moumen, N ^a   Lee, B H ^a   Barnett, J ^a   Gopalan, S ^a   Brown, B ^a   Kim, Y ^a   Young, C D ^a   Peterson, J ^a   Li, H J ^a   Zeitzoff, P M ^a   Sim, G A J H ^a   Lysaght, P ^a   Gardner, M ^a   Murto, R W ^a   Huff, H R ^a  

^a SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC GATES;

FABRICATION PROCESS; HIGH-K DIELECTRIC; HIGH-K GATE STACKS; INTEGRATION ISSUES; INTRINSIC PROPERTY; REACTIVE SPECIES; SHORT CHANNEL TRANSISTORS; TRANSISTOR PERFORMANCE;

GATE DIELECTRICS;

EID: 84932082851     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315375     Document Type: Conference Paper

References (8)

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4. G. Bersuker et al., Advanced Short-Time Thermal Processing for Si-Based CMOS Devices, ECS PV 2003-14, 417, 2003
5. C. Lim et al., 2002 ECS Fall Meeting, Salt Lake City, #377, 2002
6. Chia Ching Yeo et al., Electrochemical and Solid State Letters, 6 (11), F42, 2003
7. A. Kerber et a!., VLSI Technology Symposium, Kyoto, 2003
8. C. Young et al., IEEE-IRW Final Report, p. 28, Lake Tahoe, 2003