45 nm faces the risks and rewards of new materials

Semiconductor International

Volumn 28, Issue 1, 2005, Pages 46-50

  Singer, Peter ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; CURRENT DENSITY; DIELECTRIC MATERIALS; FERMI LEVEL; FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; POLYSILICON; RISK ASSESSMENT; SILICON COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY; TENSILE STRENGTH;

CIRCUIT DESIGN; POLYSILICON GATE; POWER MANAGEMENT; SCALING;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 18144411273     PISSN: 01633767     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Review

References (3)

1. F. Boeuf, et al., "A Conventional 45 nm CMOS Node Low-Cost Platform for General Purpose and Low Power Applications," IEDM 2004, p. 425.
2. P. Singer, "Strain Equals Gain: The New Face of Silicon," Semiconductor International, December 2004, p. 28.
3. L. Peters, "The Manufacturing Outlook for High-k/Metal Gates," Semiconductor Intimational, November 2004, p. 17.