Thermally robust dual-work function ALD-MN x MOSFETs using conventional CMOS process flow

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 186-187

  Park, D G ^a   Luo, Z J ^a   Edleman, N ^a   Zhu, W ^a   Nguyen, P ^a   Wong, K ^a   Cabral, C ^b   Jamison, P ^b   Lee, B H ^a   Chou, A ^a   Chudzik, M ^a   Bruley, J ^a   Gluschenkov, O ^a   Ronsheim, P ^a   Chakravarti, A ^a   Mitchell, R ^a   Ku, V ^a   Kim, H ^b   Duch, E ^b   Kozlowski, P ^b   D'Emic, C ^b   Narayanan, V ^b   Steegen, A ^a   Wise, R ^a   Jammy, R ^b   Rengarajan, R ^a   Ng, H ^a   Sekiguchi, A ^a   Wann, C H ^a   more..

^a IBM RESEARCH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAYER DEPOSITION; FEASIBILITY; GATE DIELECTRICS; METAL GATES;

ACTIVATION ANALYSIS; ANNEALING; DEGRADATION; GROWTH (MATERIALS); LEAKAGE CURRENTS; MOSFET DEVICES; POLYSILICON; SPUTTERING; THERMODYNAMIC STABILITY; THRESHOLD VOLTAGE; X RAY ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 4544325618     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D.-G. Park et al., IEDM Tech. Dig., p.671 (2001).
2. J. Choi et al., IEDM. Tech. Dig, p.323. (2003).
3. D.-G. Park et al., VLSI Dig., p.65 (2001).
4. S.B. Samavendam et al., IEDM. Tech. Dig., p.307 (2003).