메뉴 건너뛰기




Volumn 48, Issue 6, 2004, Pages 857-865

Nanoscale SOI MOSFETs: A comparison of two options

Author keywords

Double gate; MOSFET; Parameter sensitivity; Power; SOI; Ultra thin channel

Indexed keywords

CMOS INTEGRATED CIRCUITS; DOPING (ADDITIVES); ELECTRODES; ELECTRON TUNNELING; GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY;

EID: 1442360787     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2003.12.024     Document Type: Article
Times cited : (13)

References (42)
  • 2
    • 0042027083 scopus 로고    scopus 로고
    • A metal-insulator tunnel transistor with 16 nm channel length
    • Sasajima R., Fujimaru K., Matsumura H. A metal-insulator tunnel transistor with 16 nm channel length. Appl. Phys. Lett. 74(21):1999;3215-3217.
    • (1999) Appl. Phys. Lett. , vol.74 , Issue.21 , pp. 3215-3217
    • Sasajima, R.1    Fujimaru, K.2    Matsumura, H.3
  • 3
    • 0042527899 scopus 로고    scopus 로고
    • Observation of source-to-drain direct tunneling in 8 nm gate electrically variable shallow junction MOSFETs
    • Kawaura H., Sakamoto T., Baba T. Observation of source-to-drain direct tunneling in 8 nm gate electrically variable shallow junction MOSFETs. Appl. Phys. Lett. 76(25):2000;3810-3812.
    • (2000) Appl. Phys. Lett. , vol.76 , Issue.25 , pp. 3810-3812
    • Kawaura, H.1    Sakamoto, T.2    Baba, T.3
  • 4
    • 0000618801 scopus 로고    scopus 로고
    • Scheme for the fabrication of ultrashort channel MOSFETs
    • Appenzeller J., et al. Scheme for the fabrication of ultrashort channel MOSFETs. Appl. Phys. Lett. 77(2):2000;298-300.
    • (2000) Appl. Phys. Lett. , vol.77 , Issue.2 , pp. 298-300
    • Appenzeller, J.1
  • 5
    • 0035718151 scopus 로고    scopus 로고
    • 16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design optimization
    • Piscataway, NJ: IEEE
    • Boeuf F., et al. 16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design optimization. Techn. Dig. IEDM. 2001;637-640 IEEE, Piscataway, NJ.
    • (2001) Techn. Dig. IEDM , pp. 637-640
    • Boeuf, F.1
  • 6
    • 0035714872 scopus 로고    scopus 로고
    • 15 nm gate length planar CMOS transistor
    • Piscataway, NJ: IEEE
    • Yu B., et al. 15 nm gate length planar CMOS transistor. Techn. Dig. IEDM. 2001;937-939 IEEE, Piscataway, NJ.
    • (2001) Techn. Dig. IEDM , pp. 937-939
    • Yu, B.1
  • 7
    • 0036923438 scopus 로고    scopus 로고
    • FinFET scaling to 10 nm gate length
    • Piscataway, NJ: IEEE
    • Yu B., et al. FinFET scaling to 10 nm gate length. Techn. Dig. IEDM. 2002;251-254 IEEE, Piscataway, NJ.
    • (2002) Techn. Dig. IEDM , pp. 251-254
    • Yu, B.1
  • 8
    • 0036923554 scopus 로고    scopus 로고
    • Extreme scaling with ultra-thin Si channel MOSFETs
    • Piscataway, NJ: IEEE
    • Doris B., et al. Extreme scaling with ultra-thin Si channel MOSFETs. Techn. Dig. IEDM. 2002;267-270 IEEE, Piscataway, NJ.
    • (2002) Techn. Dig. IEDM , pp. 267-270
    • Doris, B.1
  • 9
    • 0036928692 scopus 로고    scopus 로고
    • 14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide
    • Piscataway, NJ: IEEE
    • Hokazono A., et al. 14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide. Techn. Dig. IEDM. 2002;639-642 IEEE, Piscataway, NJ.
    • (2002) Techn. Dig. IEDM , pp. 639-642
    • Hokazono, A.1
  • 11
    • 0035416636 scopus 로고    scopus 로고
    • Silicon on insulator technologies and devices: From present to future
    • Cristoloveanu S. Silicon on insulator technologies and devices: from present to future. Solid State Electron. 45(8):2001;1403-1411.
    • (2001) Solid State Electron. , vol.45 , Issue.8 , pp. 1403-1411
    • Cristoloveanu, S.1
  • 12
    • 84942082924 scopus 로고    scopus 로고
    • Electronics below 10 nm
    • J. Greer, A. Korkin, & J. Labanowski. Amsterdam: Elsevier
    • Likharev K.K. Electronics below 10 nm. Greer J., Korkin A., Labanowski J. Nano and giga challenges in microelectronics. 2003;Elsevier, Amsterdam.
    • (2003) Nano and Giga Challenges in Microelectronics
    • Likharev, K.K.1
  • 13
    • 36449008742 scopus 로고
    • Ballistic metal-oxide-semiconductor field-effect transistor
    • Natori K. Ballistic metal-oxide-semiconductor field-effect transistor. J. Appl. Phys. 76(8):1994;4879-4890.
    • (1994) J. Appl. Phys. , vol.76 , Issue.8 , pp. 4879-4890
    • Natori, K.1
  • 14
    • 0000265087 scopus 로고    scopus 로고
    • Nanoscale field-effect transistor: An ultimate size analysis
    • Pikus F.G., Likharev K.K. Nanoscale field-effect transistor: an ultimate size analysis. Appl. Phys. Lett. 71(25):1997;3661-3663.
    • (1997) Appl. Phys. Lett. , vol.71 , Issue.25 , pp. 3661-3663
    • Pikus, F.G.1    Likharev, K.K.2
  • 15
    • 0032187666 scopus 로고    scopus 로고
    • Generalized scale length for two-dimensional effects in MOSFET's
    • Frank D.J., Taur Y., Wong H.-S.P. Generalized scale length for two-dimensional effects in MOSFET's. IEEE Electron Dev. Lett. 19(10):1998;385-387.
    • (1998) IEEE Electron Dev. Lett. , vol.19 , Issue.10 , pp. 385-387
    • Frank, D.J.1    Taur, Y.2    Wong, H.-S.P.3
  • 17
    • 0033899910 scopus 로고    scopus 로고
    • Effects of the inversion-layer centroid on the performance of double-gate MOSFET's
    • López-Villanueva J.A., et al. Effects of the inversion-layer centroid on the performance of double-gate MOSFET's. IEEE Trans. Electron Dev. 47(1):2000;141-146.
    • (2000) IEEE Trans. Electron Dev. , vol.47 , Issue.1 , pp. 141-146
    • López-Villanueva, J.A.1
  • 18
    • 0033747807 scopus 로고    scopus 로고
    • Modeling of 10-nm-scale ballistic MOSFET's
    • Naveh Y., Likharev K.K. Modeling of 10-nm-scale ballistic MOSFET's. IEEE Electron Dev. Lett. 21(5):2000;242-244.
    • (2000) IEEE Electron Dev. Lett. , vol.21 , Issue.5 , pp. 242-244
    • Naveh, Y.1    Likharev, K.K.2
  • 19
    • 0035250378 scopus 로고    scopus 로고
    • Double-gate CMOS: Symmetrical versus asymmetrical-gate devices
    • Kim K., Fossum J.G. Double-gate CMOS: symmetrical versus asymmetrical-gate devices. IEEE Trans. Electron Dev. 48(2):2001;294-299.
    • (2001) IEEE Trans. Electron Dev. , vol.48 , Issue.2 , pp. 294-299
    • Kim, K.1    Fossum, J.G.2
  • 20
    • 0035714771 scopus 로고    scopus 로고
    • Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs
    • Piscataway, NJ: IEEE
    • Chang L., et al. Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs. Techn. Dig. IEDM. 2001;99-102 IEEE, Piscataway, NJ.
    • (2001) Techn. Dig. IEDM , pp. 99-102
    • Chang, L.1
  • 21
    • 0035717885 scopus 로고    scopus 로고
    • The ballistic FET: Design, capacitance and speed limit
    • Piscataway, NJ: IEEE
    • Solomon P.M., Laux S.E. The ballistic FET: design, capacitance and speed limit. Techn. Dig. IEDM. 2001;95-98 IEEE, Piscataway, NJ.
    • (2001) Techn. Dig. IEDM , pp. 95-98
    • Solomon, P.M.1    Laux, S.E.2
  • 22
    • 84961789015 scopus 로고    scopus 로고
    • Power scaling of nanoscale ballistic MOSFET circuits
    • Sverdlov V., Naveh Y., Likharev K. Power scaling of nanoscale ballistic MOSFET circuits. Proc. ISDRS. 2001;547-550.
    • (2001) Proc. ISDRS , pp. 547-550
    • Sverdlov, V.1    Naveh, Y.2    Likharev, K.3
  • 23
    • 0036253371 scopus 로고    scopus 로고
    • Essential physics of carrier transport in nanoscale MOSFETs
    • Lundstrom M., Ren Z. Essential physics of carrier transport in nanoscale MOSFETs. IEEE Trans. Electron Dev. 49(1):2002;133-141.
    • (2002) IEEE Trans. Electron Dev. , vol.49 , Issue.1 , pp. 133-141
    • Lundstrom, M.1    Ren, Z.2
  • 24
    • 0036475197 scopus 로고    scopus 로고
    • Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs
    • Ge L., Fossum J.G. Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs. IEEE Trans. Electron Dev. 49(2):2002;287-294.
    • (2002) IEEE Trans. Electron Dev. , vol.49 , Issue.2 , pp. 287-294
    • Ge, L.1    Fossum, J.G.2
  • 25
    • 18644369368 scopus 로고    scopus 로고
    • Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches
    • Venugopal R., et al. Simulating quantum transport in nanoscale transistors: real versus mode-space approaches. J. Appl. Phys. 92(7):2002;3730-3739.
    • (2002) J. Appl. Phys. , vol.92 , Issue.7 , pp. 3730-3739
    • Venugopal, R.1
  • 26
    • 0036930466 scopus 로고    scopus 로고
    • Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?
    • Piscataway, NJ: IEEE.
    • Wang J, Lundstrom M. Does source-to-drain tunneling limit the ultimate scaling of MOSFETs? In: Techn. Dig. IEDM. Piscataway, NJ: IEEE. p. 707-10.
    • Techn. Dig. IEDM , pp. 707-710
    • Wang, J.1    Lundstrom, M.2
  • 27
    • 0036923795 scopus 로고    scopus 로고
    • QUDAME simulation of 7.5 nm double-gate Si n-FET with differing access geometries
    • Piscataway, NJ: IEEE
    • Laux S.E., Kumar A., Fischetti M.V. QUDAME simulation of 7.5 nm double-gate Si n-FET with differing access geometries. Techn. Dig. IEDM. 2002;715-718 IEEE, Piscataway, NJ.
    • (2002) Techn. Dig. IEDM , pp. 715-718
    • Laux, S.E.1    Kumar, A.2    Fischetti, M.V.3
  • 30
    • 0042665554 scopus 로고    scopus 로고
    • Quantum transport in double-gate MOSFETs with complex band structure
    • Xia T., Register L.F., Banerjee S.K. Quantum transport in double-gate MOSFETs with complex band structure. IEEE Trans. Electron Dev. 50(6):2003;1511-1516.
    • (2003) IEEE Trans. Electron Dev. , vol.50 , Issue.6 , pp. 1511-1516
    • Xia, T.1    Register, L.F.2    Banerjee, S.K.3
  • 34
    • 0038417892 scopus 로고    scopus 로고
    • Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices
    • Munteanu D., Autran J.L. Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices. Solid-State Electron. 47(7):2003;1219-1225.
    • (2003) Solid-state Electron. , vol.47 , Issue.7 , pp. 1219-1225
    • Munteanu, D.1    Autran, J.L.2
  • 35
    • 0036927506 scopus 로고    scopus 로고
    • Experimental study of carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm
    • Piscataway, NJ: IEEE
    • Uchida K., Watanabe H., Kinoshita A., Koga J., Numata T., Takagi S. Experimental study of carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm. Techn. Dig. IEDM. 2002;47-50 IEEE, Piscataway, NJ.
    • (2002) Techn. Dig. IEDM , pp. 47-50
    • Uchida, K.1    Watanabe, H.2    Kinoshita, A.3    Koga, J.4    Numata, T.5    Takagi, S.6
  • 36
    • 0035718199 scopus 로고    scopus 로고
    • An experimental study of low field electron mobility in double-gate, ultra-thin SOI MOSFETs
    • Piscataway, NJ
    • Esseni D, Mastrapasqua M, Fiegna C, Celler GK, Selmi L, Sangiorgi E. An experimental study of low field electron mobility in double-gate, ultra-thin SOI MOSFETs. In: Techn Dig IEDM. Piscataway, NJ; 2001. p. 445-9.
    • (2001) Techn Dig IEDM , pp. 445-449
    • Esseni, D.1    Mastrapasqua, M.2    Fiegna, C.3    Celler, G.K.4    Selmi, L.5    Sangiorgi, E.6
  • 37
    • 0035872875 scopus 로고    scopus 로고
    • Monte Carlo simulation of double-gate silicon-on-insulator layers: The role of volume inversion
    • Gamiz F., Fischetti M.V. Monte Carlo simulation of double-gate silicon-on-insulator layers: the role of volume inversion. J. Appl. Phys. 89(10):2001;5478-5487.
    • (2001) J. Appl. Phys. , vol.89 , Issue.10 , pp. 5478-5487
    • Gamiz, F.1    Fischetti, M.V.2
  • 38
    • 0035878967 scopus 로고    scopus 로고
    • Self-consistent calculations of inversion-layer mobility in highly doped silicon-on-insulator metal-oxide-semiconductor field-effect transistors
    • Iwata H. Self-consistent calculations of inversion-layer mobility in highly doped silicon-on-insulator metal-oxide-semiconductor field-effect transistors. J. Appl. Phys. 90(2):2001;866-870.
    • (2001) J. Appl. Phys. , vol.90 , Issue.2 , pp. 866-870
    • Iwata, H.1
  • 39
    • 0042038661 scopus 로고    scopus 로고
    • Effective boundary conditions for carriers in ultrathin SOI channels
    • Sverdlov V., Oriols X., Likharev K. Effective boundary conditions for carriers in ultrathin SOI channels. IEEE Trans. Nanotechnol. 2(1):2003;59-63.
    • (2003) IEEE Trans. Nanotechnol. , vol.2 , Issue.1 , pp. 59-63
    • Sverdlov, V.1    Oriols, X.2    Likharev, K.3
  • 41
    • 0035054933 scopus 로고    scopus 로고
    • Microprocessors in the new millennium: Challenges, opportunities, and new frontiers
    • Gelsinger PP. Microprocessors in the new millennium: challenges, opportunities, and new frontiers. In: Techn. Dig. ISSCC. 2002. p. 22-5.
    • (2002) Techn. Dig. ISSCC , pp. 22-25
    • Gelsinger, P.P.1
  • 42
    • 0036508274 scopus 로고    scopus 로고
    • Power-constrained CMOS scaling limits
    • Frank D.J. Power-constrained CMOS scaling limits. IBM J. Res. Develop. 46(2/3):2002;235-244.
    • (2002) IBM J. Res. Develop. , vol.46 , Issue.2-3 , pp. 235-244
    • Frank, D.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.