Double-gate CMOS: Symmetrical- versus asymmetrical-gate devices

IEEE Transactions on Electron Devices

Volumn 48, Issue 2, 2001, Pages 294-299

  Kim, Keunwoo ^a   Possum, Jerry G ^a  

^a University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CAPACITY; COMPUTER SIMULATION; LOGIC GATES; MOSFET DEVICES; POLYSILICON; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

DOUBLE-GATE FIELD EFFECT TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 0035250378     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.902730     Document Type: Article

References (15)

1. D. J. Frank, S. E. Laux, and M. V. FischettiMonte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go? in IEDM Tech. Dig., Dec. 1992, pp. 553-556.
2. H.-S. P. Wong, D. J. Frank, and P. M. SolomonDevice design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation in IEDM Tech. Dig., Dec. 1998, pp. 40710.
3. T. Tanaka, K. Suzuki, H. Horie, and T. SugiiUltrafast operation of Vth-adjusted p+-n+ double-gate SOI MOSFET's IEEE Electron Device Lett., vol. 15, pp. 386-388, Oct. 1994.
4. J. G. Possum and Y. ChongSimulation-based assessment of 50 nm double-gate CMOS performance in Proc. IEEE Int. SOI Conf., Oct. 1998, pp. 107-108.
5. Avant!-MEDICI 4.0: Two-Dimensional Device Simulation Program. Fremont, ÇA: Avant! Corp., 1999.
6. D. Vasileska, D. K. Schröder, and D. K. FerryScaled silicon MOSFET's: Degradation of the total gate capacitance IEEE Trans. Electron Devices, vol. 44, pp. 584-587, Apr. 1997.
7. D. Vasileska and Z. Ren, SCHRED-2.0 Manual Purdue Univ., West Lafayette, IN, Feb. 2000.
8. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
9. H.-K. Lim and J. G. PossumThreshold voltage of thin-film silicon-on-insulator (SOI) MOSFET' s IEEE Trans. Electron Devices, vol. ED-30, pp. 1244-1251, Oct. 1983.
10. F. Garniz, J. A. Löpez-Villanueva, J. B. Roldan, J. E. Carceller, and P. CartujoMonte Carlo simulation of electron transport properties in extremely thin SOI MOSFET's IEEE Trans. Electron Devices, vol. 45, pp. 1122-1126, May 1998.
11. B. Majkusiak, T. Janik, and J. WalczakSemiconductor thickness effects in the double-gate SOI MOSFET IEEE Trans. Electron Devices, vol. 45, pp. 1127-1134, May 1998.
12. J. A. Löpez-Villanueva et al., Effects of inversion-layer centroid on the performance of double-gate MOSFET's IEEE Trans. Electron Devices, vol. 47, pp. 141-146, Jan. 2000.
13. K. Kim and J. G. PossumOptimal double-gate MOSFETs: Symmetrical or asymmetrical gates? in Proc. IEEE Int. SOI Conf., Oct. 1999, pp. 98-99.
14. H.-S. P. Wong, D. J. Frank, Y. Taur, and J. M. C. StorkDesign and performance considerations for sub-0.1//m double-gate SOI MOSFET's in IEDM Tech. Dig., Dec. 1994, pp. 747-750.
15. J. G. Possum, K. Kim, and Y ChongExtremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state currents IEEE Trans. Electron Devices, vol. 46, pp. 2195-2200, Nov. 1999.