Power scaling in nanoscale ballistic MOSFET circuits

2001 International Semiconductor Device Research Symposium, ISDRS 2001 - Proceedings

Volumn , Issue , 2001, Pages 547-550

  Sverdlov, V ^a   Naveh, Y ^a,b   Likharev, K ^a  

^a STONY BROOK UNIVERSITY   (United States)

^b IBM HAIFA RESEARCH LAB   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

BALLISTICS; CAPACITANCE; COMPUTER CIRCUITS; LOGIC CIRCUITS; MOSFET DEVICES; NANOTECHNOLOGY; RECONFIGURABLE HARDWARE; SEMICONDUCTOR DEVICES;

ACTIVITY FACTOR; BALLISTIC REGIME; DRIFT DIFFUSION; LOAD CAPACITANCE; MOSFET CIRCUITS; NANOSCALE MOSFETS; PHENOMENOLOGICAL MODELING; TOTAL POWER CONSUMPTION;

POWER MOSFET;

EID: 84961789015     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2001.984574     Document Type: Conference Paper

References (4)

1. International Technology Roadmap for Semiconductors, 1999 Edition, 2000 Update, available on the Web at http://public.itrs.net/.
2. Y. Naveh and K. Likharev, IEEE Electron. Dev. Lett., vol. 21, pp. 242-244, May 2000.
3. D. F. Frank et al., Proc. IEEE, vol. 259, pp. 259-288, March 2001.
4. Recently we have improved the results [3] by a self-consistent account of charge of tunneling electrons. The results of this modification are, however, minor for the cases presented here.