Nanoscale silicon MOSFETs: A theoretical study

IEEE Transactions on Electron Devices

Volumn 50, Issue 9, 2003, Pages 1926-1933

  Sverdlov, Victor A ^a   Walls, Thomas J ^a   Likharev, Konstantin K ^a  

^a STONY BROOK UNIVERSITY   (United States)

Author keywords

CMOS; Double gate transistors; Dynamic and static power; Future prospects; MOSFET; Parameter variation sensitivity; Ultrathin undoped channel

Indexed keywords

ELECTRIC NETWORK PARAMETERS; ELECTRON TUNNELING; GAIN MEASUREMENT; GATES (TRANSISTOR); NANOTECHNOLOGY; QUANTUM ELECTRONICS; QUANTUM THEORY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE;

DOUBLE GATE TRANSISTORS; DYNAMIC POWER; HIGHLY DOPED ELECTRODES; NANOSCALE TRANSISTORS; PARAMETER VARIATION SENSITIVITY; QUANTUM MECHANICAL TUNNELING; STATIC POWER; ULTRATHIN UNDOPED CHANNELS;

MOSFET DEVICES;

EID: 0042912818     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.816523     Document Type: Article

References (39)

1. R. Sasajima, K. Fujimaru, and H. Matsumura, "A metal-insulator tunnel transistor with 16 nm channel length," Appl. Phys. Lett., vol. 74, pp. 3215-3217, May 1999.
2. H. Kawaura, T. Sakamoto, and T. Baba, "Observation of source-to-drain direct tunneling in 8 nm gate electrically variable shallow junction MOSFETs," Appl. Phys. Lett., vol. 76, pp. 3810-3812, May 2000.
3. J. Appenzeller et al., "Scheme for the fabrication of ultrashort channel MOSFETs," Appl. Phys. Lett., vol. 77, pp. 298-300, July 2000.
4. F. Boeff et al., "16 nm planar NMOSFGET manufacturable within state-of-the-art CMOS process thanks to specific design optimization," inIEDM Tech. Dig., 2001, pp. 637-640.
5. B. Yu et al., "15 nm gate length planar CMOS transistor," in IEDM Tech. Dig., 2001, pp. 937-939.
6. B. Yu et al., "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, pp. 251-254.
7. B. Doris et al., "Extreme scaling with ultrathin Si channel MOSFETs," in IEDM Tech. Dig., 2002, pp. 267-270.
8. A. Hokazono et al., "14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide," in IEDM Tech. Dig., 2002, pp. 639-642.
9. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001.
10. P. M. Solomon, "Strategies at the end of CMOS scaling," in Future Trends in Microelectronics, S. Luryi, J. Xu, and A. Zaslavsky, Eds. New York: Wiley, 2002, pp. 28-42.
11. K. Likharev, "Electronics below 10 nm," in Nano and Giga Challenges in Microelectronics, J. Greer, A. Korkin, and J. Labanowski, Eds. Amsterdam, The Netherlands: Elsevier, 2003.
12. International Technology Roadmap for Semicondutors, 2001 Edition, 2002 Update [Online]. Available: http://public.itrs.net/
13. K. Natori, "Ballistic metal-oxide-semiconductor filed effect transistor," J. Appl. Phys., vol. 76, pp. 4879-4890, Oct. 1994.
14. M. S. Lundstrom, "Elementary scattering theory of the Si MOSFETs," IEEE Electron Device Lett., vol. 18, pp. 361-363, July 1997.
15. F. G. Pikus and K. K. Likharev, "Nanoscale field-effect transistor: An ultimate size analysis," Appl. Phys. Lett., vol. 71, pp. 3661-3663, Dec. 1997.
16. D. J. Frank, Y. Taur, and H.-S. P. Wong, "Generalized scale length for two-dimensional effects in MOSFETs," IEEE Electron Device Lett., vol. 19, pp. 385-387, Oct. 1998.
17. F. Assad, Z. Ren, D. Vasileska, S. Datta, and M. Lundstrom, "On the performance limits for Si MOSFETs: A theoretical study," IEEE Trans. Electron Devices, vol. 47, pp. 232-240, Jan. 2000.
18. Y. Naveh and K. K. Likharev, "Modeling of 10-nm-scale ballistic MOSFETs," IEEE Electron Device Lett., vol. 21, pp. 242-244, May 2000.
19. K. Kim and J. G. Fossum, "Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices," IEEE Trans. Electron Devices, vol. 48, pp. 294-299, Feb. 2001.
20. L. Chang et al., "Reduction of direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs," in IEDM Tech. Dig., 2001, pp. 99-102.
21. P. M. Solomon and S. E. Laux, "The ballistic FET: Design, capacitance and speed limit," in IEDM Tech. Dig., 2001, pp. 95-98.
22. M. Lundstrom and Z. Ren, "Essential physics of carrier transport in nanoscale MOSFETs," IEEE Trans. Electron. Devices, vol. 49, pp. 133-141, Jan. 2002.
23. L. Ge and J. G. Fossum, "Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs," IEEE Trans. Electron. Devices, vol. 49, pp. 287-294, Feb. 2002.
24. R. Venugopal et al., "Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches," J. Appl. Phys., vol. 92, pp. 3730-3739, Oct. 2002.
25. J. Wang and M. Lundstrom, "Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?," in IEDM Tech. Dig., 2002, pp. 707-710.
26. S. E. Laux, A. Kumar, and M. V. Fischetti, "QUDAME simulation of 7.5 nm double-gate Si n-FET with differing access geometries," in IEDM Tech. Dig., 2002, pp. 715-718.
27. A. Svizhenko and M. P. Anantram, "Role of scattering in nanotransistors," IEEE Trans. Electron Devices, vol. 50, pp. 1459-1466, June 2003.
28. V. Sverdlov X. Oriols, and K. Likharev, "Effective boundary conditions for carriers in ultrathin SOI channels," IEEE Trans. Nanotechnol., vol. 2, pp. 59-63, Mar. 2003.
29. P. M. Solomon, "On contacts to small semiconductor devices," unpublished, 1998.
30. T. J. Walls, V. A. Sverdlov, and K. K. Likharev, "Quantum mechanical modeling of advanced sub-10 nm MOSFETs," in Proc. IEEE NANO'03 Conf., Aug. 2003.
31. K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S. Takagi, "Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm," in IEDM Tech. Dig., 2002, pp. 47-50.
32. D. Esseni, M. Mastrapasqua, C. Fiegna, G. K. Celler, L. Selmi, and E. Sangiorgi, "An experimental study of low field electron mobility in double-gate, ultrathin SOI MOSFETs," in IEDM Tech. Dig., 2001, pp. 445-449.
33. F. Gamiz and M. V. Fischetti, "Monte Carlo simulation of double-gate silicon-on-insulator layers: The role of volume inversion," J. Appl. Phys., vol. 89, pp. 5478-5487, May 2001.
34. H. Iwata, "Self-consistent calculations of inversion-layer mobility in highly doped silicon-on-insulator metal-oxide-semiconductor field-effect transistors," J. Appl. Phys., vol. 90, pp. 866-870, July 2001.
35. J. A. López-Villanueva et al., "Effects of the inversion-layer centroid on the performance of double-gate MOSFETs," IEEE Trans. Electron. Devices, vol. 47, pp. 141-146, Jan. 2000.
36. D. A. Antoniadis, presented at 3rd NASA Ames Workshop Device Modeling, Tech. Rep., 1999.
37. V. Sverdlov, Y. Naveh, and K. Likharev, "Power scaling of nanoscale ballistic MOSFET circuits," in Proc. ISDRS, 2001, pp. 547-550.
38. P. P. Gelsinger, "Microprocessors in the new millennium: Challenges, opportunities, and new frontiers," in ISSCC Tech. Dig., 2002, pp. 22-25.
39. D. J. Frank, "Power-constrained CMOS scaling limits," IBM J. Res. Develop., vol. 46, pp. 235-244, Mar.-May 2002.