The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits

Nanotechnology

Volumn 17, Issue 17, 2006, Pages 4340-4351

  Bindal, Ahmet ^a   Hamedi Hagh, Sotoudeh ^a  

^a SAN JOSE STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; FIELD EFFECT TRANSISTORS; MOSFET DEVICES; NETWORKS (CIRCUITS); PROBABILITY DENSITY FUNCTION; SEMICONDUCTING SILICON; SILICON; THREE DIMENSIONAL; TRANSIENT ANALYSIS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS; WIRE;

BARRIER LOWERING; CMOS GATES; CMOS TRANSISTORS; DC CHARACTERISTICS; DEVICE GEOMETRIES; EFFECTIVE CHANNEL LENGTHS; EXPLORATORY STUDIES; FULL ADDER CIRCUITS; FULL ADDERS; LAYOUT AREAS; METAL GATES; MOS TRANSISTORS; NAND GATES; OFF CURRENTS; OUTPUT CAPACITANCES; PMOS TRANSISTORS; POWER DISSIPATIONS; SILICON WIRES; SIMULATION RESULTS; SOI TECHNOLOGIES; TRANSIENT PERFORMANCES; TRANSIENT RESPONSES; TRANSIENT TIMES; UNDOPED BODIES; XOR GATES;

ADDERS;

NANOWIRE; SILICON;

ARTICLE; ELECTRIC POTENTIAL; GEOMETRY; MATHEMATICAL COMPUTING; NONHUMAN; PRIORITY JOURNAL; SEMICONDUCTOR; SIMULATION; THREE DIMENSIONAL IMAGING;

EID: 55149089100     PISSN: 09574484     EISSN: 13616528     Source Type: Journal    
DOI: 10.1088/0957-4484/17/17/010     Document Type: Article

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