A novel low power low voltage full adder cell

International Symposium on Image and Signal Processing and Analysis, ISPA

Volumn 1, Issue , 2003, Pages 454-458

  Chang, Chip Hong ^a   Zhang, Mingyan ^a   Gu, Jiangmin ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Adders; Arithmetic; Circuit simulation; CMOS logic circuits; Energy efficiency; Energy measurement; Logic circuits; Logic design; Low voltage; Power generation

Indexed keywords

CELLS; CIRCUIT SIMULATION; CYTOLOGY; DELAY CIRCUITS; DESIGN; DIGITAL ARITHMETIC; ELECTRIC POWER MEASUREMENT; ENERGY EFFICIENCY; IMAGE ANALYSIS; IMAGE PROCESSING; INTEGRATED CIRCUIT DESIGN; INTEGRATING CIRCUITS; LOGIC CIRCUITS; LOGIC DESIGN; LOW POWER ELECTRONICS; POWER GENERATION; PRODUCT DESIGN; SIGNAL PROCESSING;

ARITHMETIC CIRCUIT; CMOS LOGIC CIRCUITS; DIRECT MEASUREMENT; LOW POWER LOW VOLTAGES; LOW POWER-DELAY PRODUCT; LOW VOLTAGES; POWER DELAY PRODUCT; RESTORATION CIRCUITS;

ADDERS;

EID: 34248657511     PISSN: 18455921     EISSN: 18492266     Source Type: Conference Proceeding    
DOI: 10.1109/ISPA.2003.1296940     Document Type: Conference Paper

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