A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 923-926

  Kikuchi, T ^a   Moriya, S ^a   Nakatsuka, Y ^a   Matsuoka, H ^a   Nakazato, K ^b   Nishida, A ^c   Chakihara, H ^c   Matsuoka, M ^c   Moniwa, M ^c  

^a HITACHI LTD   (Japan)

^b HITACHI CAMBRIDGE LABORATORY   (United Kingdom)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA REDUCTION; ELECTRIC BATTERIES; EQUIVALENT CIRCUITS; MOS CAPACITORS; POLYSILICON; RANDOM ACCESS STORAGE; SPEED; POLYCRYSTALLINE MATERIALS;

6T-SRAM; DESIGN RULES; OPERATION SPEED; STACKED VERTICAL MOS (SVMOS);

MOSFET DEVICES;

6T-SRAM; 6T-SRAMS; DEVICES INTEGRATION; HIGH SPEED; NODE-BASED; NOVEL TECHNIQUES; OPERATION SPEED; SI MOSFET;

EID: 21644470779     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. H.Matsuoka et al., Symposium of VLSI tech., pp.234, 2004
2. J.Y.W. Seto, J.Appl.Phys.46, pp. 5247, 1975
3. M. Kanda et al, Symp, VLSI Tech. Digest, pp. 13, 2003