A review of 0.18-μm full adder performances for tree structured arithmetic circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 6, 2005, Pages 686-694

  Chang, Chip Hong ^a   Gu, Jiangmin ^a   Zhang, Mingyan ^a,b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b TECH Semiconductor Singapore PTE LTD   (Singapore)

Author keywords

Adders; Cmos digital integrated circuits; Digital arithmetic; Logic devices

Indexed keywords

ARITHMETIC CIRCUITS; CMOS DIGITAL INTEGRATED CIRCUITS; WALLACE-DADDA TREE; WIRING INTERCONNECTIONS;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; ELECTRIC POTENTIAL; LOGIC CIRCUITS; LOGIC DEVICES; VLSI CIRCUITS;

ADDERS;

EID: 23744492075     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.848806     Document Type: Review

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