Nano-wires for room temperature operated hybrid CMOS-NANO integrated circuits

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Ecoffey, Serge ^a   Pott, Vincent ^a   Bouvet, Didier ^a   Mazza, Marco ^a   Mahapatra, Santanu ^a   Schmid, Alexandre ^a   Leblebici, Yusuf ^a   Declercq, Michel J ^a   Ionescu, Adrian M ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144432921     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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4. S. Ecoffey et al., "A Hybrid CMOS-SET Co-Fabrication Platform using Nano-Grain Polysilicon Wires," Proceedings of Micro- and Nano-Engineering International Conference, pp. 148-149, Sept., 2004.
5. S. Ecoffey et al., "LPCVD Deposition of Nanograin Polysilicon Ultra-Thin Films," Journal of Nanotechnology, vol. 13, no. 3, pp. 290-293, June, 2002.
6. K. Yano et al., "Single-Electron Memory for Giga-to-Tera Bit Storage," Proceedings of the IEEE, vol. 87, no. 4, pp. 633-651, April, 1999.
7. A. M. Ionescu et al., "Hybrid CMOS-SET Architecture with Coulomb Blockade Oscillations and High Current Drive," IEEE Electron Device Letters (EDL), vol. 25, no. 6, pp. 411-413, June, 2004.