A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 657-660

  Bai, P ^a   Auth, C ^a   Balakrishnan, S ^a   Bost, M ^a   Brain, R ^a   Chikarmane, V ^a   Heussner, R ^a   Hussein, M ^a   Hwang, J ^a   Ingerly, D ^a   James, R ^a   Jeong, J ^a   Kenyon, C ^a   Lee, E ^a   Lee, S H ^a   Lindert, N ^a   Liu, M ^a   Ma, Z ^a   Marieb, T ^a   Murthy, A ^a   Nagisetty, R ^a   Natarajan, S ^a   Neirynck, J ^a   Ott, A ^a   Parker, C ^a   Sebastian, J ^a   Shaheed, R ^a   Sivakumar, S ^a   Steigerwald, J ^a   Tyagi, S ^a   Weber, C ^a   Woolery, B ^a   Yeoh, A ^a   Zhang, K ^a   Bohr, M ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; DIELECTRIC MATERIALS; EPITAXIAL GROWTH; LEAKAGE CURRENTS; MASKS; MICROPROCESSOR CHIPS; MOS DEVICES; NICKEL COMPOUNDS; SILICON COMPOUNDS; STATIC RANDOM ACCESS STORAGE; STRAIN;

APSM MASKS; DIELECTRIC PATTERNING; MOORE'S LAW; ULTRA-SHALLOW JUNCTIONS;

LOGIC GATES;

EID: 21644432592     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. K. Mistry, et al., Symp. VLSI Tech. Dig., 2004.
2. T. Ghani, et al., IEDM Tech. Dig., pp. 197-200, 2003.