Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits

IEEE Transactions on Semiconductor Manufacturing

Volumn 15, Issue 1, 2002, Pages 9-18

  Semenov, Oleg ^b   Pradzynski, Andrzej ^a,c   Sachdev, Manoj ^a,b  

^a IEEE

^b UNIVERSITY OF WATERLOO   (Canada)

^c Gennum Corporation   (Canada)

Author keywords

Band to band tunneling; CMOS ICs reliability; Gate induced leakage current; Standard logic cells layout

Indexed keywords

COMPUTER SIMULATION; DYNAMIC RANDOM ACCESS STORAGE; GATES (TRANSISTOR); LEAKAGE CURRENTS; PROM; VLSI CIRCUITS;

GATE INDUCED DRAIN LEAKAGE (GIDL);

CMOS INTEGRATED CIRCUITS;

EID: 0036474749     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.983439     Document Type: Article

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