A new dual-material double-gate (DMDG) nanoscale SOI MOSFET - Two-dimensional analytical modeling and simulation

IEEE Transactions on Nanotechnology

Volumn 4, Issue 2, 2005, Pages 260-268

  Reddy, G Venkateshwar ^a   Kumar, M Jagadesh ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

Double gate (DG); Drain induced barrier lowering (DIBL); Dual material gate (DMG); IV model; Silicon on insulator (SOI) MOSFET; Two dimensional (2 D) modeling

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); MATHEMATICAL MODELS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

DOUBLE GATE (DG); DRAIN INDUCED BARRIER LOWERING (DIBL); DUAL MATERIAL GATES (DMG); TWO-DIMENSIONAL (2-D) MODELING;

NANOTECHNOLOGY;

EID: 15844418329     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2004.837845     Document Type: Article

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