Leakage power analysis of 25-nm double-gate CMOS devices and circuits

IEEE Transactions on Electron Devices

Volumn 52, Issue 5, 2005, Pages 980-986

  Kim, Keunwoo ^a   Das, Koushik K ^a   Joshi, Rajiv V ^a   Chuang, Ching Te ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Double gate (DG) device; Drain induced barrier lowering (DIBL); Latch; Leakage power

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; POWER ELECTRONICS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS;

DG TECHNOLOGY; DOUBLE GATE (DG) DEVICE; DRAIN INDUCED BARRIER LOWERING (DIBL); DYNAMIC CIRCUITS; LEAKAGE POWER ANALYSIS; STATIC CIRCUITS;

GATES (TRANSISTOR);

EID: 18844457099     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.846317     Document Type: Article

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