A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55 μm2 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 285-288

  Nakai, Satoshi ^a   Kojima, Manabu ^a   Misawa, Nobuhiro ^a   Miyajima, Motoshu ^a   Asai, Satoru ^a   Inagaki, Satoshi ^a   Iba, Yoshihisa ^a   Ohba, Takayuki ^a   Kase, Masataka ^a   Kitada, Hideki ^a   Satoh, Shigeo ^a   Shimizu, Noriyoshi ^a   Sugiura, Iwao ^a   Sugimoto, Fumitoshi ^a   Setta, Yuji ^a   Tanaka, Tetsu ^a   Tamura, Naoyoshi ^a   Nakaishi, Masafumi ^a   Nakata, Yoshihiro ^a   Nakahira, Junya ^a   Nishikawa, Nobuyuki ^a   Hasegawa, Akihiro ^a   Fukuyama, Shunichi ^a   Fujita, Kazushi ^a   Hosaka, Kimihiko ^a   Horiguchi, Naoto ^a   Matsuyama, Hideya ^a   Minami, Takayoshi ^a   Minamizawa, Masaharu ^a   Morioka, Hiroshi ^a   Yano, Ei ^a   Yamaguchi, Akihisa ^a   Watanabe, Kiyoshi ^a   Nakamura, Tomoji ^a   Sugii, Toshihiro ^a   more..

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CATALYST ACTIVITY; COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; ELASTIC MODULI; EVAPORATION; FREQUENCIES; INTERCONNECTION NETWORKS; MOBILE TELECOMMUNICATION SYSTEMS; MULTIMEDIA SYSTEMS; NANOSTRUCTURED MATERIALS; PARAMETER ESTIMATION; PORE SIZE; PRESSURE MEASUREMENT; STRENGTH OF MATERIALS; STRESS ANALYSIS; TRANSISTORS;

LOW-LEAKAGE TRANSISTORS; POWER CONSUMPTION;

CMOS INTEGRATED CIRCUITS;

EID: 17644444817     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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7. S. Kondo et al., "Low-pressure CMP for reliable porous low-k/Cu integration," International Interconnect Tech. Conf., pp. 86-88, 2003.