A 65nm-node, Cu Interconnect Technology Using Porous Sioch Film (k=2.5) Covered with Ultra-Thin, Low-k Pore Seal (k=2.7)

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 845-848

  Tada, M ^a   Harada, Y ^a   Tamura, T ^b   Inoue, N ^a   Ito, F ^a   Yoshiki, M ^a   Ohtake, H ^a   Narihiro, M ^a   Tagami, M ^a   Ueki, M ^a   Hijioka, K ^a   Abe, M ^a   Takeuchi, T ^a   Saito, S ^a   Onodera, T ^a   Furutake, N ^a   Arai, K ^a   Fujii, K ^b   Hayashi, Y ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITANCE; COPPER; DIELECTRIC FILMS; ELECTRIC RESISTANCE; FOURIER TRANSFORM INFRARED SPECTROSCOPY; INTERFACES (MATERIALS); METALLIZING; METALLORGANIC CHEMICAL VAPOR DEPOSITION; POROUS SILICON; ULTRATHIN FILMS;

INTER-METAL DIELECTRICS (IMD); THERMAL DESORPTION SPECTROSCOPY (TDS);

ELECTRIC CONNECTORS;

EID: 17644448440     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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6. Y. Harada et. al., 2002 SSDM, p180 (2002).
7. M. Tada, et al., 2003 IITC, p256 (2003).