Performance analysis of low-power 1-bit CMOS full adder cells

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 1, 2002, Pages 20-29

  Shams, Ahmed M ^a,c   Darwish, Tarek K ^a,b   Bayoumi, Magdy A ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Addition; Arithmetic; Full adder; Low power; Performance analysis

Indexed keywords

ADDER CELLS;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; ENERGY UTILIZATION; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; SWITCHING;

ADDERS;

EID: 0036476973     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.988727     Document Type: Article

References (15)

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13. An enhanced low-power pipelined multiplier-accumulator for DSP applications