On the feasibility of nanoscale triple-gate CMOS transistors

IEEE Transactions on Electron Devices

Volumn 52, Issue 6, 2005, Pages 1159-1164

  Yang, Ji Woon ^a   Fossum, Jerry G ^a  

^a University of Florida   (United States)

Author keywords

Gate layout area; Multigate MOSFETs; Nanoscale CMOS; Short channel effects (SCEs)

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); MOSFET DEVICES; PARTIAL DIFFERENTIAL EQUATIONS; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY;

GATE LAYOUT AREA; MULTIGATE MOSFETS; NANOSCALE CMOS; SHORT CHANNEL EFFECTS (SCES);

CMOS INTEGRATED CIRCUITS;

EID: 21044447633     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.848109     Document Type: Article

References (17)

1. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
2. B. Doris et al., "Extreme scaling with ultrathin Si channel MOSFETs," in IEDM Tech. Dig., Dec. 2002, pp. 267-270.
3. J. Kedzierski et al., "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation," in IEDM Tech. Dig., Dec. 2002, pp. 247-250.
4. S. Xiong and J. Bokor, "Sensitivity of double-gate and FinFET devices to process variations," IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2255-2260, Nov. 2003.
5. V. P. Trivedi, J. G. Fossum, and F. Gámiz, "A compact QM-based mobility model for nanoscale ultra-thin-body CMOS devices," in IEDM Tech. Dig., Dec. 2004, pp. 763-766.
6. V. P. Trivedi and J. G. Fossum, "Scaling fully depleted SOI CMOS," IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2095-2103, Oct. 2003.
7. V. P. Trivedi, J. G. Fossum, and M. M. Chowdhury, "Nanoscale FinFETs with gate-source/drain underlap," IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 56-62, Jan. 2005.
8. B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalierous, T. Linton, A. Murthy, R. Rios, and R. Chau, "High performance fully-depleted tri-gate CMOS transistors," IEEE Electron Device Lett., vol. 24, no. 4, pp. 263-265, Apr. 2003.
9. B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalierous, T. Linton, R. Rios, and R. Chau, "Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout," in Symp. VLSI Tech. Dig., Jun. 2003, pp. 133-134.
10. J. G. Fossum, J.-W. Yang, and V. P. Trivedi, "Suppression of corner effects in triple-gate MOSFETs," IEEE Electron Device Lett., vol. 24, no. 12, pp. 745-747, Dec. 2003.
11. "Davinci-2003.06 User Guide," Synopsys, Inc., Durham, NC, 2003.
12. G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E. C.-C. Kan, "FinFET design considerations based on 3-D simulation and analytical modeling," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1411-1419, Aug. 2002.
13. Z. Krivokapic, V. Moroz, W. Maszara, and M.-R. Lin, "Locally strained ultrathin channe125 nm narrow FDSOI devices with metal gate and mesa isolation," in IEDM Tech. Dig., Dec. 2003, pp. 445-448.
14. "International Technology Roadmap for Semiconductors," Semiconductor Industry Association, San Jose, CA, 2001.
15. S.-H. Kim, J. G. Fossum, and V. P. Trivedi, "Bulk inversion in FinFETs and the implied insignificance of the effective gate width," in Proc. IEEE Int. SOI Conf., Oct. 2004, pp. 145-147.
16. J. P. Colinge, M. H. Gao, A. Romano-Rodríguez, H. Maes, and C. Claeys, "Silicon-on-insulator 'gate-all-around device'," in IEDM Tech. Dig., Dec. 1990, pp. 595-598.
17. H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, "Impact of surrounding gate transistor (SGT) for ultrahigh-density LSIs," IEEE Trans. Electron Devices, vol. 38, no. 3, pp. 573-578, Mar. 1991.