Transport properties of sub-10-nm planar-bulk-CMOS devices

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 429-432

  Wakabayashi, Hitoshi ^a   Ezaki, Tatsuya ^a   Hane, Masami ^a   Ikezawa, Takeo ^b   Sakamoto, Toshitsugu ^b   Kawaura, Hisao ^b   Yamagami, Shigeharu ^a   Ikarashi, Nobuyuki ^a   Takeuchi, Kiyoshi ^a   Yamamoto, Toyoji ^a   Mogami, Tohru ^a  

^a System Devices Research Laboratories   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRON TUNNELING; GATES (TRANSISTOR); MOSFET DEVICES; OSCILLATIONS; QUANTUM THEORY; THRESHOLD VOLTAGE; VOLTAGE CONTROL; CMOS INTEGRATED CIRCUITS; TEMPERATURE;

DIRECT TUNNELING CURRENTS; DRAIN INDUCED TUNNELING MODULATION; NEGATIVE-DIFFERENTIAL TRANSCONDUCTANCE (NDT); PEAK-TO-VALLEY CURRENT RATIOS (PVCR); SYSTEMS-ON-CHIP (SOC);

CMOS INTEGRATED CIRCUITS; TRANSPORT PROPERTIES;

BULK CMOS DEVICES; CMOS DEVICES; DIRECT TUNNELING CURRENTS; DRAIN INDUCED TUNNELING MODULATION; DRAIN REGION; MODULATION EFFECTS; MOS-FET; SOURCE AND DRAINS; SOURCE REGION; SUB 10 NM;

EID: 21644446426     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. M. Iwai, et al., "45nm CMOS Platform Technology (CMOS6) with High Density Embedded Memories," in Symp. VLSI Tech., 2004, pp. 12-13.
2. Bruce Doris, et al., "Extreme Scaling with Ultra-Thin Si Channel MOSFETs," in IEDM Tech. Dig., 2002, pp. 267-270.
3. Hitoshi Wakabayashi, Nobuyuki Ikezawa, Mitsuru Narihiro, Koh-ichi Arai, Tomoko Matsuda, Kiyoshi Takeuchi, Toyoji Yamamoto, Yukinori Ochiai, and Tohru Mogami "Sub-10-nm Physical-Gate-Length Bulk-CMOS Technology," in IEDM Tech. Dig., 2003, pp. 989-991.
4. Hisao Kawaura, et al., "Transport Properties in Sub-10-nm-gate EJ-MOSFETs," in Extended Abstracts of the 1999 Int. Conf. on Solid State Dev. and Mat. (SSDM) 1999, pp. 20-21.
5. Jing Wang et al., "Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?," in IEDM Tech. Dig., 2002, pp. 707-710.
6. F. Bœuf, et al., "Controlled Single Electron Effects in Nanometric MOSFETs," in Silicon Nanoelectronics Workshop, 2002, pp. 61-62.
7. S. Monfray, et al., "Coulomb-Blockade in Nanometric Si-film SON MOSFETs," in Silicon Nanoelectronics Workshop, 2003, pp. 74-75.
8. International Technology Roadmap for Semiconductors 2003, http://public.itrs.net/.
9. Ken Uchida, et al., "Programmable Single-Electron Transistor Logic for Future Low-Power Intelligent LSI: Proposal and Room-Temperature Operation," in IEEE Transactions on Electron Devices, Vol. 50, No. 7, July 2003, pp. 1623-1630.
10. R. Tsu and L. Esaki, "Tunneling in a finite superlattice," in Appl. Phys. Lett., Vol. 22, No. 11, 1973, pp. 562-564.