A conventional 45nm CMOS node low-cost platform for general purpose and low power applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 425-428

  Boeuf, F ^a   Arnaud, F ^a   Tavel, B ^b   Duriez, B ^b   Bidaud, M ^b   Gouraud, P ^a   Chaton, C ^c   Morin, P ^a   Todeschini, J ^b   Jurdit, M ^c   Pain, L ^c   De Jonghe, V ^b   Basso, M T ^a   Sotta, D ^b   Wacquant, F ^a   Rosa, J ^a   El Farhane, R ^b   Jullian, S ^b   Bicais Lepinay, N ^a   Bernard, H ^a   Bustos, J ^a   Manakli, S ^a   Gaillardin, M ^a   Grant, J ^d   Skotnicki, T ^a   more..

^a STMICROELECTRONICS   (France)

^b NXP SEMICONDUCTORS   (Netherlands)

^c CEA LETI   (France)

^d FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHIZATION; CALIBRATION; COMPUTER ARCHITECTURE; DIELECTRIC MATERIALS; LEAKAGE CURRENTS; OSCILLATORS (ELECTRONIC); POWER SUPPLY CIRCUITS; NITROGEN COMPOUNDS; SILICON COMPOUNDS;

FERMI-PINNING PHENOMENON; HIGH-K; MASTAR MODEL; PROCESS INDUCED STRAIN (PIS); STRAINED-SI;

CMOS INTEGRATED CIRCUITS;

45NM NODE; CMOS NODES; GATE OXIDE; HIGH-VOLTAGES; LOW POWER APPLICATION; LOW-COSTS; PROCESS INDUCED STRAINS; SHALLOW-JUNCTIONS;

EID: 21644452674     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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