Communication architecture optimization: Making the shortest path shorter in regular networks-on-chip

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Ogras, Umit Y ^a   Marculescu, Radu ^a   Lee, Hyung Gyu ^b   Chang, Naehyuck ^b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; OPTIMIZATION; SOFTWARE PROTOTYPING;

COMMUNICATION ARCHITECTURE; INTER-NODE DISTANCES; NETWORK-ON-CHIP (NOC);

COMPUTER ARCHITECTURE;

EID: 34047150878     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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