Networks on silicon: Blessing or nightmare?

Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002

Volumn , Issue , 2002, Pages 196-200

  Wielage, P ^a   Goossens, K ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Bandwidth; Clocks; Costs; Delay effects; Laboratories; Moore's Law; Silicon; Very large scale integration; Wires; Wiring

Indexed keywords

BANDWIDTH; CLOCKS; COSTS; ELECTRIC WIRING; LABORATORIES; MICROPROCESSOR CHIPS; NETWORK ROUTING; SILICON; SYSTEMS ANALYSIS; VLSI CIRCUITS; WIRE;

DEEP SUB-MICRON; DELAY EFFECTS; GLOBAL INTERCONNECTS; LIMITING PERFORMANCE; LONG DISTANCE COMMUNICATION; MOORE'S LAW; ON CHIP COMMUNICATION; SIGNAL INTEGRITY;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84949672053     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2002.1115369     Document Type: Conference Paper

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