A methodology for design, modeling, and analysis of networks-on-chip

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1778-1781

  Xu, Jiang ^a   Wolf, Wayne ^a   Henkel, Joerg ^b   Chakradhar, Srimat ^c  

^a PRINCETON UNIVERSITY   (United States)

^b UNIVERSITY OF KARLSRUHE   (Germany)

^c NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC; BUS-BASED; CIRCUIT-LEVEL MODELS; DESIGN COMPILER; DESIGN FLOWS; FLOORPLAN; NETWORKS ON CHIPS; NOC DESIGN; PERFORMANCE ANALYSIS; REAL COMMUNICATION; SILICON AREA; SOC DESIGNS;

BIOLOGICAL MATERIALS; CIRCUIT SIMULATION; LOGIC CIRCUITS; LOGIC DESIGN; METAL REFINING; MICROPROCESSOR CHIPS; SPICE; SWITCHING CIRCUITS;

ELECTRIC NETWORK TOPOLOGY;

EID: 33847228171     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464953     Document Type: Conference Paper

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