The impact of communication on the scalability of the data-parallel video encoder on MPSoC

2006 International Symposium on System-on-Chip, SOC

Volumn , Issue , 2006, Pages

  Salminen, Emo ^a   Kangas, Tero ^a   Hämäläinen, Timo D ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; MULTIPROCESSING SYSTEMS; SCALABILITY; SIGNAL ENCODING; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS;

APPLICATION MODELING; COMMUNICATION BANDWIDTH; COMPLEX APPLICATIONS; COMPUTATIONAL LOADS; DESIGN SPACE EXPLORATION; MODEL AND SIMULATION; MULTIPROCESSOR SYSTEM ON CHIPS; PROCESSING ELEMENTS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 50049127075     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSOC.2006.321965     Document Type: Conference Paper

References (10)

1. A. Andriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. A. Zeferino, "SPIN: a scalable, packet switched, on-chip micro-network," in DATE, Munich, Germany, March 2003, pp. 70-73.
2. D. Culler, J. Singh, and A. Gupta, Parallel Computer Architecture - A Hardware/Software Approach. Morgan Kaufmann, 1998.
3. W. J. Dally and B. Towles, Principles and practices of interconnection networks. Morgan Kaufmann Publishers, 2004.
4. R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, vol. 89, no. 4, pp. 490-504, 2001.
5. A. A. Jerraya, "Long term trends for embedded system design," in Euromicro Symposium on Digital System Design (DSD), Rennes, France, September 2004, pp. 20-26.
6. T. Kangas, K. Kuusilinna, and T. D. Hämäläinen, "Scalable architecture for SoC video encoders," accepted to Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, 2006.
7. T. Kangas, J. Riihimäki, E. Salminen, K. Kuusilinna, and T. D. Hämäläinen, "Using a communication generator in SoC architecture exploration," in Symposium on System-on-Chip, Tampere, Finland, November 2003, pp. 105-108.
8. P. Pande, C. Grecu, A. I. M. Jones, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Transactions on Computers, vol. 54, no. 8, pp. 1025-1040, August 2005.
9. C. Rowen, Engineering the Complex SoC, 1st ed. Upper Saddle River, NJ, USA: Prentice Hall PTR, 2004.
10. E. Salminen, T. Kangas, J. Riihimki, V. Lahtinen, K. Kuusilinna, and T. D. Hämäläinen, "Hibi communication network for system-on-chip," Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 43, no. 2, May 2006.