Automated bus generation for multiprocessor SoC design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 11, 2004, Pages 1531-1549

  Ryu, Kyeong Keol ^a   Mooney III, Vincent J ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Bus architecture; Bus generation; Design space exploration; Synthesis; System on a chip (SoC)

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER NETWORKS; DATABASE SYSTEMS; OPTIMIZATION; SYNTHESIS (CHEMICAL); TRANSMITTERS; VLSI CIRCUITS;

BUS ARCHITECTURE; BUS GENERATION; DESIGN SPACE EXPLORATIONS; SYSTEM-ON-A-CHIP (SOC);

MULTIPROCESSING SYSTEMS;

EID: 8344242181     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.835119     Document Type: Article

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