A systemc test environment for spin network

Proceedings of the International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2006

Volumn , Issue , 2006, Pages 449-453

  Charlery, H ^a,b   Greiner, A ^a,b  

^a SORBONNE UNIVERSITÉ   (France)

^b UNIVERSITÉ PIERRE ET MARIE CURIE   (France)

Author keywords

Network on chip; SPIN; SystemC; VCI; Wrapper

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; MICROELECTRONICS; PACKET SWITCHING; PROGRAM PROCESSORS;

MICRO NETWORKS; NETWORK ON CHIPS; ON-CHIP ARCHITECTURES; SYSTEMC;

NETWORK ARCHITECTURE;

EID: 41549142400     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. P. Guerrier et A. Greiner, "A Generic Architecture for On-Chip Packet-Switched Interconnections", Proceeding of the Design Automation and Test in Europe Conference 2000 (DATE 2000), March 2000.
2. A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez et C. A. Zeferino, "SPIN: a Scalable, Packet Switched, On-chip Micro-network", Proceeding of the Design Automation and Test in Europe Designers'Forum 2003 (DATE 2003), Munich, March 2003.
3. Open Microprocessor Systems Initiative, "PI-Bus Draft Standard Specification", ftp://www.omimo.be/ftp/standard/omi324.ps, 1994.
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