-
2
-
-
3042588782
-
-
DAC, New Orleans, USA
-
W. Cesario, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A.A. Jerraya, M. Diaz-Nava, "Component-Based Design Approach for Multicore SoCs", DAC, New Orleans, USA, 2002.
-
(2002)
Component-Based Design Approach for Multicore SoCs
-
-
Cesario, W.1
Baghdadi, A.2
Gauthier, L.3
Lyonnard, D.4
Nicolescu, G.5
Paviot, Y.6
Yoo, S.7
Jerraya, A.A.8
Diaz-Nava, M.9
-
3
-
-
21244442444
-
-
available online at
-
M. Coppola, S. Curaba, M. Grammatikakis, G. Maruccia, F. Papariello, "On-Chip Communication Network: User Manual v1.0.1", available online at http://occn.sourceforge.net/occn_user_manual.html
-
On-Chip Communication Network: User Manual v1.0.1
-
-
Coppola, M.1
Curaba, S.2
Grammatikakis, M.3
Maruccia, G.4
Papariello, F.5
-
4
-
-
0034848111
-
On-chip communication architecture for OC-768 network processors
-
Las Vegas, NV, June
-
F. Karim, A. Nguyen, S. Dey, and R. Rao. "On-chip communication architecture for OC-768 network processors", Proceedings of Design Automation Conference, Las Vegas, NV, June 2001, pp. 678-683.
-
(2001)
Proceedings of Design Automation Conference
, pp. 678-683
-
-
Karim, F.1
Nguyen, A.2
Dey, S.3
Rao, R.4
-
5
-
-
34047185449
-
-
DAC, San Diego, USA, June
-
S.-I. Han, A. Baghdadi, M. Bonaciu, S.-I. Chae, A.A. Jerraya, "An Efficient Scalable and Flexible Data Transfer Architecture for Multiprocessor SoC with Massive Distributed Memory", DAC, San Diego, USA, June 2004.
-
(2004)
An Efficient Scalable and Flexible Data Transfer Architecture for Multiprocessor SoC with Massive Distributed Memory
-
-
Han, S.-I.1
Baghdadi, A.2
Bonaciu, M.3
Chae, S.-I.4
Jerraya, A.A.5
-
6
-
-
33646916009
-
-
DATE, Munich, Germany
-
S. Mahadevan, F. Angiolini, M. Storgaard, R. G. Olsen, J. Sparsø, J. Madsen, "A Network Traffic Generator Model for Fast Network-on-Chip Simulation", DATE, Munich, Germany, 2005, pp. 780-785 Vol. 2
-
(2005)
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
, vol.2
, pp. 780-785
-
-
Mahadevan, S.1
Angiolini, F.2
Storgaard, M.3
Olsen, R.G.4
Sparsø, J.5
Madsen, J.6
-
7
-
-
33847226043
-
-
SOC2003, Tampere, Finland, November
-
T. Salminen and J.-P. Soininen, "Evaluating application mapping using network simulation.", SOC2003, Tampere, Finland, November 2003.
-
(2003)
Evaluating application mapping using network simulation
-
-
Salminen, T.1
Soininen, J.-P.2
-
9
-
-
52149090515
-
Network Processing Challenges and an Experimental NPU Platform
-
P. Paulin, C. Pilkington, E. Bensoudane. "Network Processing Challenges and an Experimental NPU Platform", DATE 2003, Designers' Forum, p. 64.
-
DATE 2003, Designers' Forum
, pp. 64
-
-
Paulin, P.1
Pilkington, C.2
Bensoudane, E.3
-
10
-
-
3042511814
-
-
Paris, France
-
M. Loghi, F. Angiolini, D. Bertozzi, L. Benini, R. Zafalon, Analyzing On-Chip Communication in a MPSoC Environment, DATE, Paris, France, 2004, pp. 752-757 Vol. 2
-
(2004)
Analyzing On-Chip Communication in a MPSoC Environment, DATE
, vol.2
, pp. 752-757
-
-
Loghi, M.1
Angiolini, F.2
Bertozzi, D.3
Benini, L.4
Zafalon, R.5
-
11
-
-
3042558166
-
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
-
S. Pestana, E. Rijpkema, A. Radulescu, K. Goossens, O. P. Gangwal, "Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach", DATE 2004: 764-769.
-
(2004)
DATE
, pp. 764-769
-
-
Pestana, S.1
Rijpkema, E.2
Radulescu, A.3
Goossens, K.4
Gangwal, O.P.5
-
12
-
-
0035368837
-
System-Level Performance Analysis for Designing On-Chip Communication Architectures
-
June
-
K.Lahiri, A.Raghunathan, S.Dey, "System-Level Performance Analysis for Designing On-Chip Communication Architectures", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol.20, no.6, pp.768-783, June 2001.
-
(2001)
IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems
, vol.20
, Issue.6
, pp. 768-783
-
-
Lahiri, K.1
Raghunathan, A.2
Dey, S.3
|