A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2006, Issue , 2006, Pages 657-664

  Richardson, Thomas D ^a   Nicopoulos, Chrysostomos ^a   Park, Dongkook ^a   Narayanan, Vijaykrishnan ^a   Xie, Yuan ^a   Das, Chita ^a   Degalahal, Vijay ^a  

^a The Center for Nanotechnology Education and Utilization   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INJECTION RATES; NETWORKS ON CHIP (NOC).; ON CHIP NETWORKS; POWER CONSUMPTION;

BUSBARS; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; PACKET NETWORKS; TIME DIVISION MULTIPLE ACCESS;

INTERCONNECTION NETWORKS;

EID: 33748554106     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2006.10     Document Type: Conference Paper

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