Flexible bus and NoC performance analysis with configurable synthetic workloads

Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

Volumn , Issue , 2006, Pages 681-688

  Thid, Rikard ^a   Sander, Ingo ^a   Jantsch, Axel ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

Benchmark; Bus; NoC; Performance analysis; Simulation; Synthetic workloads

Indexed keywords

NETWORKS (CIRCUITS); PETRI NETS; STOCHASTIC MODELS; TELECOMMUNICATION SYSTEMS;

COMMUNICATION INFRASTRUCTURE; DESIGN SPACE; PERFORMANCE ANALYSIS; SYNTHETIC WORKLOADS;

MICROPROCESSOR CHIPS;

EID: 34547983104     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.52     Document Type: Conference Paper

References (19)

1. A. Alameldeen and D. Wood. Addressing Workload Variability in Architectural Simulations. IEEE Micro, 23(6):94-98, November - December 2003.
2. M. P. C. Lee and H. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In Proceedings of the 30th Annual International Symposium on Microarchitecture, December 1997.
3. W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2004.
4. S. González Pestana, E. Rijpkema, A. Rǎdulescu, K. Goossens, and O. P. Gangwal. Cost-Performance Tradeoffs in Networks on Chip: A Simulation-Based Approach. In Proceedings of the conference on Design, automation and test in Europe, volume 2, pages 764-769, February 2004.
5. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. MiBench: A free, commercially representative embedded benchmark suite. In IEEE 4th Annual Workshop on Workload Characterization, pages 3-14, December 2001.
6. K. Lahiri, A. Raghunathan, and S. Dey. Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. In Fourteenth International Conference on VLSI Design, pages 29-35, January 2001.
7. W. E. Leland, M. S. Taqqu, W. Willinger, and D. V. Wilson. On the self-similar nature of Ethernet traffic (extended version). IEEE/ACM Transactions on Networking, 2(1): 1-15, 1994.
8. S. Mahadevan, F. Angiolini, M. Storgaard, R. G. Olsen, J. Sparso, and J. Madsen. A Network Traffic Generator Model for Fast Network-on-Chip Simulation. In Proceedings of the conference on Design, Automation and Test in Europe, pages 780-785, 2005.
9. J. Mahdavi and V. Paxson. RFC2678-2681. http://www.ietf.org/rfc.html, September 1999.
10. M. A. Marsan, G. C. G. Balbo, S. Donatelli, and G. Franceschinis. Modelling with Generalized Stochastic Petri Nets. Wiley Series in Parallel Computing. John Wiley and Sons, 1995.
11. M. Millberg, E. Nilsson, R. Thid, S. Kumar, and A. Jantsch. The Nostrum backbone - a communication protocol stack for networks on chip. In Proceedings of the International Conference on VLSI Design, pages 693-696, January 2004.
12. K. Sadron, M. Martonosi, D. I. August, M. D. Hill, D. J. Lilja, and V. S. Pai. Challenges in Computer Architecture Evaluation. IEEE Computer, 36(8): 30-36, August 2003.
13. J. Voldman, B. Mandelbrot, L. Hoevel, J. Knight, and P. Rosenfeld. Fractal Nature of Software-Cache Interaction. IBM Journal of Research and Development, 27(2): 164-170, March 1983.
14. M. Wang, N. H. Chan, S. Papadimitriou, C. Faloutsos, and T. Madhyastha. Data Mining Meets Performance Evaluation: Fast Algorithms for Modeling Bursty Traffic. In Proceedings of the 18th International Conference on Data Engineering, pages 507-516, February 2002.
15. R. P. Weicker. Dhrystone: A Synthetic Systems Programming Benchmark. Communications of the ACM, 27(10): 1013-1030, October 1984.
16. D. Wiklund, S. Sathe, and D. Liu. Network on chip simulations for benchmarking. In Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, pages 269-274. IEEE Computer Society, July 2004.
17. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 24-36, June 1995.
18. T. T. Ye, L. Benini, and G. D. Micheli. Packetization and routing analysis of on-chip multiprocessor networks. Journal of Systems Architecture, 50(2-3):81-104, 2004.
19. D. Zwillinger, editor. CRC Standard Mathematical Tables and Formulae. Chemical Rubber Company Press, 30th edition, 1995.