Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 483-488

  Usami, Kimiyoshi ^a   Lgarashi, Mutsunori ^a   Ishikawa, Takashi ^a   Kanazawa, Masahiro ^a   Takahashi, Masafumi ^a   Hamada, Mototsugu ^a   Arakida, Hideho ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; ELECTRIC POWER SUPPLIES TO APPARATUS; VOLTAGE SCALING; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK SYNTHESIS; FLIP FLOP CIRCUITS; POWER CONVERTERS; STANDARDS; VOLTAGE STABILIZING CIRCUITS;

DESIGN METHODOLOGY; DIFFERENT VOLTAGES; FULLY AUTOMATED; LOW-POWER DESIGN; MPEG-4 CODEC; SUPPLY VOLTAGES; ULTRA LOW POWER;

DESIGN; LSI CIRCUITS;

CODEC; MOTION PICTURE EXPERTS GROUP (MPEG) STANDARDS;

EID: 0031639539     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Igarashi, M., et al. "A Low-power Design Method Using Multiple Supply Voltages", ACM/IEEE ISLPED-97, pp.3641, Aug. 1997.
2. Kuroda, T., et al., "A High-Speed Low-Power 0.3um CMOS Gate-Array with Variable Threshold Voltage (VT) Scheme", IEEE CICC-96, pp.53-56, May 1996.
3. Suzuki, K., et al., "A 300M1PS/W RISC Core Processor with Variable Supply-Voltage Scheme in Variable Threshold- Voltage CMOS", IEEE CICC-97, pp.587-590, May 1997.
4. Takahashi, M., et al, "A 60mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable Supply-Voltage Scheme", ISSCC Digest of Technical Papers, pp.36-37, Feb. 1998.
5. Usami, K., et al., "Clustered Voltage Scaling Technique for Low-Power Design", ACM/IEEE ISLPD-95, pp.3-8, April 1995.
6. Usami, K., et al., "Automated Low-power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor", IEEE CICC-97, pp. 131-134, May 1997.