High-reliability, low-energy microarchitecture synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 12, 1998, Pages 1273-1280

  Dasgupta, Aurobindo ^a   Karri, Ramesh ^a  

^a University of Massachusetts   (United States)

Author keywords

Electromigration; High level synthesis; Low power

Indexed keywords

EID: 0000053207     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.736567     Document Type: Article

References (31)

1. A. Chandrakasan, M. Potkonjak, J. Rabaey, and R. Brodersen, "HYPERLP: A system for power minimization using architectural transformations," in Proc. Int. Conf. CAD, Nov. 1992, pp. 300-303.
2. A. Raghunathan and N.K. Jha, "An iterative improvement algorithm for low power data path synthesis," in Proc. Int. Conf. Computer Design, Oct. 1995, pp. 597-602.
3. J.S. Arzigian, "Aluminum electromigration lifetime variations with linewidth: The effects of changing stress conditions," in Proc. Int. Reliability Physics Symp., 1983.
4. H.B. Bakoglu, Circuits, Interconnection and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
5. J.M. Black, "Electromigration - A brief survey and some recent results," in Proc. IEEE Electron Devices, 1969, vol. 16, pp. 338-342.
6. A. Chandrakasan, T. Sheng, and R.W. Brodersen, "Low power CMOS digital design," J. Solid-State Circuits, vol. 27, pp. 473-484, Apr. 1992.
7. K. Chao and D.F. Wong, "Low power considerations in floorplan design," in Proc. Int. Workshop Low Power Design, Apr. 1993, pp. 45-50.
8. T. Chou, K. Roy, and S. Prasad, "Estimation of circuit activity considering signal correlations and simultaneous switching," in Proc. Int. Conf. CAD, Nov. 1994, pp. 300-303.
9. C. Hu, "The Berkeley reliability simulator BERT: An IC reliability simulator," Microelectron.J., vol. 23, pp. 97-102, 1992.
10. A. Christou, Electromigration and Electronic Device Degradation. New York: Wiley, 1994.
11. J. Cho and C.V. Thompson, "The grain size dependence of electromigration induced failures in narrow interconnects," Appl. Phys. Lett., vol. 54, no. 25, p. 2577, 1989.
12. J. Clement, E. Atakov, and J. Lyoyd, "Electromigration reliability of VLSI interconnect," Digital Tech.J., vol. 4, no. 2, 1992.
13. A. Dasgupta and R. Karri, "Simultaneous scheduling and binding for power minimization during microarchitecture synthesis," in Proc. Int. Symp. Low Power Design, Apr. 1995, pp. 140-143.
14. S. Devadas, H.F. Jyu, K. Kuetzer, and S. Malik, "Statistical timing analysis in combinational circuits," in Proc. Int. Conf. Computer Design, Oct. 1992, pp. 38-33.
15. A. Ghosh, S. Devadas, K. Kuetzer, and J. White, "Estimation of average switching activity in combinational and sequential circuits," in Proc. 29th Design Automation Conf., June 1992, pp. 253-259.
16. L. Goodby, A. Orailoglu, and P. Chau, "High-level synthesis for low power design," in Proc. Int. Conf. Computer Design, Oct. 1994, pp. 323-326.
17. J.E. Hall et al., "SPIDER - A CAD system for modeling VLSI metallization patterns," in Proc. Int. Conf. CAD, Nov. 1986, pp. 220-223.
18. T.S. Hohol and L. A. Glasser, "RELIC: A reliability simulator for integrated circuits," in Proc. Int. Conf. CAD, Nov. 1986, pp. 224-227.
19. T. Kwok, "Effects of grain growth and grain structure on electromigration lifetime in Al-Cu submicron interconnects," in Proc. 4th Multilevel Interconnection Conf., 1985, p. 83.
20. B. Liew, N. Cheung, and C. Hu, "Projecting interconnect electromigration lifetime for arbitrary current waveforms," IEEE Trans. Electron Devices, vol. 37, pp. 1343-1351, May 1990.
21. J.A. Maiz, "Characterization of electromigration under bidirectional (BC) and pulsed unidirectional (PDC) currents," in Proc. Int. Reliability Physics Symp., 1989, pp. 220-228.
22. F.N. Najm, R. Burch, P. Yang, and I. Hajj, "CREST - A current estimator for CMOS circuits," in Proc. Int. Conf. CAD, Nov. 1988, pp. 204-207.
23. F.N. Najm, "Transition density, a stochastic measure of activity in digital circuits," in Proc. 28th Design Automation Conf., 1991, pp. 644-649.
24. C. Papachristou, M. Spining, and M. Nourani, "A multiple clocking scheme for low power RTL design," in Proc. Int. Symp. Low Power Design, Apr. 1995, pp. 121-129.
25. P.G. Paulin and J. P. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Trans. Computer-Aided Design, vol. 8, pp. 661-679, June 1989.
26. S. Raje and M. Sarrafzadeh, "Variable voltage scheduling," in Proc. Int. Symp. Low Power Design, Apr. 1995, pp. 125-130.
27. K. Roy and S. Prasad, "SYCLOP: Synthesis of CMOS logic for low power application," in Proc. Int. Conf. Computer Design, Oct. 1993, pp. 464-467.
28. H.A. Schafft and T. C. Grant, "Electromigration and current density dependence," in Proc. Int. Reliability Physics Symp., 1985.
29. M.A. Schuette and J. R. Barr, "Embedded systems design for low energy consumption," in Proc. Int. Conf. CAD, Nov. 1994, pp. 534-540.
30. C. Svenson and D. Liu, "A power estimation tool and prospects of power savings in CMOS VLSI chips," in Proc. Int. Workshop Low Power Design, Apr. 1994, pp. 171-176.
31. C. Tsui, M. Pedram, and A.M. Despain, "Power efficient technology decomposition and mapping under an extended power consumption model," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1110-1122, Sept. 1994.