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1
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0345253177
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Memory and data-path mapping for image and video applications
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F. Catthoor and L. Svensson (eds.), Boston, MA: Kluwer
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W. Geurts, F. Franssen, M. van Swaaij, F. Catthoor, H. De Man, and M. Moonen, “Memory and data-path mapping for image and video applications,” in Application-driven architecture synthesis, F. Catthoor and L. Svensson (eds.), Boston, MA: Kluwer, 1993, pp. 143-166.
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Application-Driven Architecture Synthesis
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Geurts, W.1
Franssen, F.2
Van Swaaij, M.3
Catthoor, F.4
De Man, H.5
Moonen, M.6
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2
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0012111580
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Background memory management for the synthesis of algebraic algorithms on multiprocessor DSP chips
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Munich, Germany
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I. Verbauwhede, F. Catthoor, J. Vandewalle, and H. De Man, “Background memory management for the synthesis of algebraic algorithms on multiprocessor DSP chips,” Proc. VLSI’89, lnt. Conf. on VLSI, Munich, Germany, Aug. 1989, pp. 209-218.
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(1989)
Proc. VLSI’89, Lnt. Conf. On VLSI
, pp. 209-218
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Verbauwhede, I.1
Catthoor, F.2
Vandewalle, J.3
De Man, H.4
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3
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0028754935
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Global communication and memory optimizing transformations for low power signal processing systems
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J. Rabaey, P. Chau, and J. Eldon (eds.). New York, NY: IEEE Press
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F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. De Man, “Global communication and memory optimizing transformations for low power signal processing systems,” in VLSI Signal Processing VII, J. Rabaey, P. Chau, and J. Eldon (eds.). New York, NY: IEEE Press, 1994, pp. 178-187.
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(1994)
VLSI Signal Processing VII
, pp. 178-187
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Catthoor, F.1
Franssen, F.2
Wuytack, S.3
Nachtergaele, L.4
De Man, H.5
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4
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0029290289
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Portable video-on-demand in wireless communication
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April
-
T. H. Meng, B. Gordon, E. Tsem, and A. Hung, “Portable video-on-demand in wireless communication,” specialissue on “Low power design” of the Proceedings of the IEEE, voi. 83, no. 4, April 1995, pp. 659-680.
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Low Power Design of the Proceedings of the IEEE
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, pp. 659-680
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Meng, T.H.1
Gordon, B.2
Tsem, E.3
Hung, A.4
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5
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0028722375
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Power analysis of embedded software: A first step towards software power minimization
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Dec
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V. Tiwari, S. Malik, and A. Wolfe, “Power analysis of embedded software: A first step towards software power minimization,” IEEE Trans, on VLSI Systems, voi. 2, no. 4, Dec. 1994, pp. 437-445.
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IEEE Trans, on VLSI Systems
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, pp. 437-445
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Tiwari, V.1
Malik, S.2
Wolfe, A.3
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6
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33747695328
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Automating high-level control flow transformations for DSP memory management
-
K. Yao, R. Jain, and W. Przytula (eds.), New York, NY: IEEE Press
-
M. van Swaaij, F. Franssen, F. Catthoor, and H. De Man, “Automating high-level control flow transformations for DSP memory management,” in VLSI Signal Processing V, K. Yao, R. Jain, and W. Przytula (eds.), New York, NY: IEEE Press, 1992, pp. 397-406.
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(1992)
VLSI Signal Processing V
, pp. 397-406
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Van Swaaij, M.1
Franssen, F.2
Catthoor, F.3
De Man, H.4
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7
-
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0028026376
-
Control flow optimization for fast system simulation and storage minimization
-
Paris, France
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F. Franssen, L. Nachtergaele, H. Samsom, F. Catthoor, and H. De Man, “Control flow optimization for fast system simulation and storage minimization,” Proc. 5th ACM/IEEE Europ. Design and Test Conf, Paris, France, Feb. 1994, pp. 20-24.
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(1994)
Proc. 5Th ACM/IEEE Europ. Design and Test Conf
, pp. 20-24
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-
Franssen, F.1
Nachtergaele, L.2
Samsom, H.3
Catthoor, F.4
De Man, H.5
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8
-
-
0028602659
-
Loop transformation methodology for fixed-rate video, image and telecom processing applications
-
Aug
-
F. Catthoor, W. Geurts, and H. De Man, “Loop transformation methodology for fixed-rate video, image and telecom processing applications,” Proc. Intnl. Conf. on Applic.-Spec. Array Processors, Aug. 1994, pp. 427-438.
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(1994)
Proc. Intnl. Conf. On Applic.-Spec. Array Processors
, pp. 427-438
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-
Catthoor, F.1
Geurts, W.2
De Man, H.3
-
9
-
-
0029474262
-
Memory organization for video algorithms on programmable signal processors
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Austin TX, Oct
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E. De Greef, F. Catthoor, and H. De Man, “Memory organization for video algorithms on programmable signal processors,” Proc. IEEE lnt. Conf. on Computer Design, Austin TX, Oct. 1995, pp. 552-557.
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(1995)
Proc. IEEE Lnt. Conf. On Computer Design
, pp. 552-557
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-
De Greef, E.1
Catthoor, F.2
De Man, H.3
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10
-
-
0031997237
-
System-level power optimization of video codecs on embedded cores: A systematic approach
-
Boston, MA: Kluwer
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L. Nachtergaele, D. Moolenaar, B. Vanhoof, F. Catthoor, and H. De Man, “System-level power optimization of video codecs on embedded cores: A systematic approach,” Journal of VLSI Signal Processing, Boston, MA: Kluwer, 1998.
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(1998)
Journal of VLSI Signal Processing
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-
Nachtergaele, L.1
Moolenaar, D.2
Vanhoof, B.3
Catthoor, F.4
De Man, H.5
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11
-
-
84878664523
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System-level memory management for weakly parallel image processing, “Lecture notes in computer science series
-
France, Springer Verlag
-
K. Danckaert, F. Catthoor, and H. De Man, “System-level memory management for weakly parallel image processing, “Lecture notes in computer science” series, Proc. EuroPar Conference, Lyon, France, Springer Verlag, August 1996, pp. 217-225.
-
(1996)
Proc. Europar Conference, Lyon
, pp. 217-225
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-
Danckaert, K.1
Catthoor, F.2
De Man, H.3
-
12
-
-
0029292281
-
Power conscious CAD tools and methodologies: A perspective, specialissue on “Low power design” of the
-
D. Singh, J. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, and T. Mozdzen, “Power conscious CAD tools and methodologies: A perspective,” specialissue on “Low power design” of the Proceedings of the IEEE, voi. 83, no. 4, April 1995, pp. 570-594.
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(1995)
Proceedings of the IEEE
, vol.83
, Issue.4
, pp. 570-594
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-
Singh, D.1
Rabaey, J.2
Pedram, M.3
Catthoor, F.4
Rajgopal, S.5
Sehgal, N.6
Mozdzen, T.7
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13
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-
0027577076
-
A 6-ns 1-Mb CMOS SRAM with latched sense amplifier
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Apr
-
T. Seki, E. Itoh, C. Furukawa, I. Maeno, T. Ozawa, H. Sano, and N. Suzuki, “A 6-ns 1-Mb CMOS SRAM with latched sense amplifier,” IEEE J. of Solid-state Circuits, voi. SC-28, no. 4, Apr. 1993, pp. 478-483.
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IEEE J. Of Solid-State Circuits
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Seki, T.1
Itoh, E.2
Furukawa, C.3
Maeno, I.4
Ozawa, T.5
Sano, H.6
Suzuki, N.7
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14
-
-
52549121309
-
System exploration for custom low power data storage and transfer
-
K. Parili and T. Nishitani (eds.), New York: Marcel Dekker, Inc
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F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, and P. Slock, “System exploration for custom low power data storage and transfer,” chapter in “Digital signal processing for multimedia systems,” K. Parili and T. Nishitani (eds.), New York: Marcel Dekker, Inc., 1998.
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(1998)
Digital Signal Processing for Multimedia Systems
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-
Catthoor, F.1
Wuytack, S.2
De Greef, E.3
Balasa, F.4
Slock, P.5
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15
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-
0003197260
-
The SUIF compiler for scalable parallel machines
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S. Amarasinghe, J. Anderson, M. Lam, and C. Tseng, “The SUIF compiler for scalable parallel machines,” Proc. of the 7th SIAM Conf on Parallel Proc. for Scientific Computing, 1995.
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(1995)
Proc. Of the 7Th SIAM Conf on Parallel Proc for Scientific Computing
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Amarasinghe, S.1
Anderson, J.2
Lam, M.3
Tseng, C.4
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16
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0027541302
-
Automatic program parallelisation
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Feb
-
U. Banerjee, R. Eigenmann, A. Nicolau, and D. Padua, “Automatic program parallelisation,” Proc. of the IEEE, invited paper, voi. 81, no. 2, Feb. 1993.
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(1993)
Proc. Of the IEEE
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Banerjee, U.1
Eigenmann, R.2
Nicolau, A.3
Padua, D.4
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17
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0027799223
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Allocation of multiport memories for hierarchical data streams
-
Santa Clara, CA, Nov
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P. Lippens, J. van Meerbergen, W. Verhaegh, and A. van der Werf, “Allocation of multiport memories for hierarchical data streams,” Proc. IEEE Int. Conf. Comp. Aided Design, Santa Clara, CA, Nov. 1993.
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(1993)
Proc. IEEE Int. Conf. Comp. Aided Design
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Lippens, P.1
Van Meerbergen, J.2
Verhaegh, W.3
Van Der Werf, A.4
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18
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0028076680
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An algorithm for array variable clustering
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Paris, France, Feb
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L. Ramachandran, D. Gajski, and V. Chaiyakul, “An algorithm for array variable clustering,” Proc. 5th ACM/IEEE Europ. Design and Test Conf, Paris, France, Feb. 1994, pp. 262-266.
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Proc. 5Th ACM/IEEE Europ. Design and Test Conf
, pp. 262-266
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Ramachandran, L.1
Gajski, D.2
Chaiyakul, V.3
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19
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0028565177
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Minimization of memory traffic in high-level synthesis
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San Diego, CA, June
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D. Kolson, A. Nicolau, and N. Dutt, “Minimization of memory traffic in high-level synthesis,” Proc. 31st ACM/IEEE Design Automation Conf, San Diego, CA, June 1994, pp. 149-154.
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Proc. 31St ACM/IEEE Design Automation Conf
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Kolson, D.1
Nicolau, A.2
Dutt, N.3
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20
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0029231165
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Optimizing power using transformations
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Jan
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A. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W. Broder-sen, “Optimizing power using transformations,” IEEE Trans, on Comp.-aided Design, vol. CAD-14, no. 1, Jan. 1995, pp. 12-30.
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IEEE Trans, on Comp.-Aided Design
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Chandrakasan, A.1
Potkonjak, M.2
Mehra, R.3
Rabaey, J.4
Broder-Sen, R.W.5
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21
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0029244586
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VLSI architectures for video compression—a survey
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Feb
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P. Pirsch, N. Demassieux, and W. Gehrke, “VLSI architectures for video compression—a survey,” Proc. of the IEEE, invited paper, voi. 83, no. 2, Feb. 1995, pp. 220-246.
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Proc. Of the IEEE
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Pirsch, P.1
Demassieux, N.2
Gehrke, W.3
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22
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0029254527
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A single chip videophone encoder/decoder
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Feb
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M. Harrand, M. Henry, P. Chaisemartin, P. Mougeat, Y. Durand, A. Tournier, R. Wilson, J. Herluison, J. Langchambon, J. Bauer, M. Runtz, and J. Bulone, “A single chip videophone encoder/decoder,” Proc. IEEE Int. Solid-State Circ. Conf, Feb. 1995, pp. 292-293.
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Proc. IEEE Int. Solid-State Circ. Conf
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Harrand, M.1
Henry, M.2
Chaisemartin, P.3
Mougeat, P.4
Durand, Y.5
Tournier, A.6
Wilson, R.7
Herluison, J.8
Langchambon, J.9
Bauer, J.10
Runtz, M.11
Bulone, J.12
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23
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0030169056
-
Transforming set data types to power optimal data structures
-
June
-
S. Wuytack, F. Catthoor, and H. De Man, “Transforming set data types to power optimal data structures,” IEEE Trans, on Comp.-aided Design, voi. CAD-15, no. 6, June 1996, pp. 619-629.
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(1996)
IEEE Trans, on Comp.-Aided Design
, vol.CAD-15
, Issue.6
, pp. 619-629
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Wuytack, S.1
Catthoor, F.2
De Man, H.3
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24
-
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0022983013
-
A CAD environment for the thorough analysis, simulation and characterisation of VLSI implementable DSP systems
-
Port Chester, NY
-
L. Claesen, F. Catthoor, H. De Man, J. Vandewalle, S. Note, and K. Mertens, “A CAD environment for the thorough analysis, simulation and characterisation of VLSI implementable DSP systems,” Proc. IEEE Int. Conf. on Computer Design, Port Chester, NY, Oct. 1986, pp. 72-75.
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(1986)
Proc. IEEE Int. Conf. On Computer Design
, pp. 72-75
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Claesen, L.1
Catthoor, F.2
De Man, H.3
Vandewalle, J.4
Note, S.5
Mertens, K.6
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25
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-
84947919147
-
Global approach for compiled bit-true simulation of DSP systems
-
France, Springer Verlag
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L. De Coster, M. Engels, R. Lauwereins, and J. Peperstraete, “Global approach for compiled bit-true simulation of DSP systems,” “Lecture notes in computer science” series, Lyon, France, Springer Verlag, August 1996, pp. 236-239.
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Lecture Notes in Computer Science Series, Lyon
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De Coster, L.1
Engels, M.2
Lauwereins, R.3
Peperstraete, J.4
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26
-
-
0027663292
-
Modeling multi-dimensional data and control flow
-
Sep
-
F. Franssen, F. Balasa, M. van Swaaij, F. Catthoor, and H. De Man, “Modeling multi-dimensional data and control flow,” IEEE Trans, on VLSI systems, voi. 1, no. 3, Sep. 1993, pp. 319-327.
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(1993)
IEEE Trans, on VLSI Systems
, vol.1
, Issue.3
, pp. 319-327
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Franssen, F.1
Balasa, F.2
Van Swaaij, M.3
Catthoor, F.4
De Man, H.5
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27
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2542541191
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System-level data-flow transformation exploration and power-area trade-offs demonstrated on video codecs, specialissue on Systematic trade-off analysis in signal processing systems design”
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F. Catthoor, M. Janssen, L. Nachtergaele, and H. De Man, “System-level data-flow transformation exploration and power-area trade-offs demonstrated on video codecs,” specialissue on Systematic trade-off analysis in signal processing systems design” in J. of VLSI Signal Processing, 1997.
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(1997)
J. Of VLSI Signal Processing
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Catthoor, F.1
Janssen, M.2
Nachtergaele, L.3
De Man, H.4
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28
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84935364892
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SynGuide: An environment for doing interactive correctness preserving transformations
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L. Eggermont, P. Dewilde, E. Deprettere, and J. van Meerbergen (eds.), New York, NY: IEEE Press
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H. Samsom, L. Claesen, and H. De Man, “SynGuide: an environment for doing interactive correctness preserving transformations,” in VLSI Signal Processing VI, L. Eggermont, P. Dewilde, E. Deprettere, and J. van Meerbergen (eds.), New York, NY: IEEE Press, 1993, pp. 269-277.
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VLSI Signal Processing VI
, pp. 269-277
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Samsom, H.1
Claesen, L.2
De Man, H.3
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29
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0028751083
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Verification of loop transformations for real time signal processing applications
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J. Rabaey, P. Chau, and J. Eldon (eds.), New York, NY: IEEE Press
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H. Samsom, F. Franssen, F. Catthoor, and H. De Man, “Verification of loop transformations for real time signal processing applications,” in VLSI Signal Processing VII, J. Rabaey, P. Chau, and J. Eldon (eds.), New York, NY: IEEE Press, 1994, pp. 269-277.
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(1994)
VLSI Signal Processing VII
, pp. 269-277
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Samsom, H.1
Franssen, F.2
Catthoor, F.3
De Man, H.4
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30
-
-
0030690709
-
Formalized methodology for data reuse exploration in hierarchical memory mappings
-
Monterey, Aug
-
J. P. Diguet, S. Wuytack, F. Catthoor, and H. De Man, “Formalized methodology for data reuse exploration in hierarchical memory mappings,” accepted for Proc. IEEE Intnl. Symp. on Low Power Design, Monterey, Aug. 1997.
-
(1997)
Proc. IEEE Intnl. Symp. On Low Power Design
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Diguet, J.P.1
Wuytack, S.2
Catthoor, F.3
De Man, H.4
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31
-
-
0031342466
-
Memory size reduction through storage order optimization for embedded parallel multimedia applications
-
Proc. Workshop on “Parallel Processing and Multimedia,” Geneva, Switzerland
-
E. De Greef, F. Catthoor, and H. De Man, “Memory size reduction through storage order optimization for embedded parallel multimedia applications,” Intnl. Parallel Proc. Symp. (IPPS) in Proc. Workshop on “Parallel Processing and Multimedia,” Geneva, Switzerland, April 1997.
-
(1997)
Intnl. Parallel Proc. Symp. (IPPS)
-
-
De Greef, E.1
Catthoor, F.2
De Man, H.3
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32
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-
0030378208
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Flow graph balancing for minimizing the required memory bandwidth
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S. Wuytack, F. Catthoor, G. De Jong, B. Lin, and H. De Man, “Flow graph balancing for minimizing the required memory bandwidth,” Proc. 9th ACM/IEEE Intnl. Symp. on System-Level Synthesis, 1996, pp. 127-132.
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(1996)
Proc. 9Th ACM/IEEE Intnl. Symp. On System-Level Synthesis
, pp. 127-132
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-
Wuytack, S.1
Catthoor, F.2
De Jong, G.3
Lin, B.4
De Man, H.5
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33
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85051985978
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An adaptive algorithm for motion compensated colour image coding
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C. Lin and S. Kwatra, “An adaptive algorithm for motion compensated colour image coding,” Proc. IEEE Globecom, 1984, pp. 47.1.1-4.
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Proc. IEEE Globecom, 1984, Pp. 47
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Lin, C.1
Kwatra, S.2
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34
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0027555637
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VLSI architecture of a SMDS/ATM router
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Y. Therasse, G. H. Petit, and M. Delvaux, “VLSI architecture of a SMDS/ATM router,” Annales des Télécommunications, vol. 48, no. 3-4, 1993, pp. 166-180.
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(1993)
Annales Des Télécommunications
, vol.48
, Issue.3-4
, pp. 166-180
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Therasse, Y.1
Petit, G.H.2
Delvaux, M.3
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35
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2542556528
-
Low power data transfer and storage exploration for H.263 video decoder system
-
L. Nachtergaele, F. Catthoor, B. Kapoor, D. Moolenaar, and S. Janssen, “Low power data transfer and storage exploration for H.263 video decoder system,” accepted for SpecialIssue on Very Low-Bit Rate Video Coding of IEEE Journal on Selected Areas in Communications, voi. 15, 1997.
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(1997)
Very Low-Bit Rate Video Coding of IEEE Journal on Selected Areas in Communications
, pp. 15
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Nachtergaele, L.1
Catthoor, F.2
Kapoor, B.3
Moolenaar, D.4
Janssen, S.5
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36
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0001151864
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Background memory area estimation for multi-dimensional signal processing systems
-
June
-
F. Balasa, F. Catthoor, and H. De Man, “Background memory area estimation for multi-dimensional signal processing systems,” IEEE Trans, on VLSI Systems, vol. 3, no. 2, June 1995, pp. 157-172.
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(1995)
IEEE Trans, on VLSI Systems
, vol.3
, Issue.2
, pp. 157-172
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Balasa, F.1
Catthoor, F.2
De Man, H.3
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