High-level power modeling, estimation, and optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 11, 1998, Pages 1061-1079

  Macii, Enrico ^a,b   Pedram, Massoud ^a,b   Somenzi, Fabio ^a,b  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF COLORADO   (United States)

Author keywords

Behavioral and logic synthesis; Low power design; Power management

Indexed keywords

COMPUTATIONAL METHODS; DIGITAL INTEGRATED CIRCUITS; ELECTRONICS PACKAGING; ENERGY DISSIPATION; ENERGY MANAGEMENT; ENERGY UTILIZATION; FORMAL LOGIC; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PERSONAL COMPUTERS; SEMICONDUCTING SILICON; WIRELESS TELECOMMUNICATION SYSTEMS;

REGISTER-TRANSFER LEVELS (RTL);

VLSI CIRCUITS;

EID: 0032202596     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.736181     Document Type: Article

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