Energy optimization of multilevel cache architectures for RISC and CISC processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 2, 1998, Pages 299-308

  Ko, Uming ^b   Balsara, Poras T ^a,c   Nanda, Ashwini K ^d  

^a IEEE

^b TEXAS INSTRUMENTS   (United States)

^c The University of Texas at Dallas   (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Cache architecture; High performance; Low power; Multilevel; Processor

Indexed keywords

COMPUTER SYSTEMS PROGRAMMING; OPTIMIZATION; REDUCED INSTRUCTION SET COMPUTING;

COMPLEX INSTRUCTION SET COMPUTER (CISC) MACHINES;

BUFFER STORAGE;

EID: 0032097825     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.678891     Document Type: Article

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