Low-power memory mapping through reducing address bus activity

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 3, 1999, Pages 309-320

  Panda, Preeti Ranjan ^b   Dutt, Nikil D ^a,c  

^a IEEE

^b SYNOPSYS INC   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PERIPHERAL EQUIPMENT; HEURISTIC METHODS; MICROPROCESSOR CHIPS; STORAGE ALLOCATION (COMPUTER);

ADDRESS BUS; LOW-POWER MEMORY MAPPING;

DATA STORAGE EQUIPMENT;

EID: 0032641123     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.784092     Document Type: Article

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