Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 8, Issue 6, 1998, Pages 719-733

  De Greef, Eddy ^b   Catthoor, Francky ^a,b   De Man, Hugo ^a,b  

^a IEEE

^b IMEC   (Belgium)

Author keywords

Buffer size reduction; Power optimization; Program transformations; Synchronization; Video and image processing

Indexed keywords

ALGORITHMS; BUFFER STORAGE; ENERGY UTILIZATION; OPTIMIZATION; STORAGE ALLOCATION (COMPUTER); SYNCHRONIZATION;

PROGRAM TRANSFORMATIONS; PSEUDOREGULAR MULTIMEDIA SUBSYSTEMS;

MULTIMEDIA SYSTEMS;

EID: 0032184461     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.728414     Document Type: Article

References (34)

1. F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. De Man, "Global communication and memory optimizing transformations for low power signal processing systems," in Proc. IEEE Workshop VLSI Signal Processing, La Jolla, CA, Oct. 1994. Also in VLSI Signal Processing VII, J. Rabaey, P. Chau, and J. Eldon, Eds. New York: IEEE Press, 1994, pp. 178-187.
2. T. Seki, E. Itoh, C. Furukawa, I. Maeno, T. Ozawa, H. Sano, and N. Suzuki, "A 6-ns 1-Mb CMOS SRAM with latched sense amplifier," IEEE J. Solid-State Circuits, vol. 28, pp. 478-483, Apr. 1993.
3. K. Itoh, K. Sasaki, and Y. Nakagome, "Trends in low-power ram circuit technologies" Proc. IEEE (Special Issue on Low Power Electronics), vol. 83, pp. 524-543, Apr. 1995.
4. F. Catthoor, W. Geurts, and H. De Man, "Loop transformation methodology for fixed-rate video, image and telecom processing applications," in Proc. Int. Conf. Application Specific Array Processors, San Francisco, CA, Aug. 1994, pp. 427-438.
5. V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards: Algorithms and Architectures. Boston, MA: Kluwer Academic, 1995.
6. T. Halfhill and J. Montgomery, "Chip fashion: Multi-media chips," Byte Mag., pp. 171-178, Nov. 1995.
7. P. Feautrier, "Dataflow analysis of array and scalar references," Int. J. Parallel Programming, vol. 20, no. 1, pp. 23-53, 1991.
8. W. Pugh, "The omega test: A fast and practical integer programming algorithm for dependence analysis," in Proc. Supercomputing '91, Nov. 1991.
9. M. Cierniak and W. Li, "Unifying data and control transformations for distributed shared memory machines," in Proc. SIGPLAN '95 Conf. Programming Language Design and Implementation, La Jolla, CA, 1995, pp. 205-217.
10. A. Darte, T. Risset, and Y. Robert, "Loop nest scheduling and transformations," in J. J. Dongarra et al., Eds., Advances in Parallel Computing 6. Amsterdam: North-Holland, 1993, pp. 309-332, environments and tools for parallel scientific computing ed.
11. W. Li and K. Pingali, "Access normalization: Loop restructuring for NUMA compilers," in Proc. 5th Int. Conf. Architectural Support for Programming Languages and Operating Syst., 1992.
12. B. K. Bose, P. M. Hansen, C. Lee, and D. A. Patterson, "Fast scientific computation in CMOS VLSI shared-memory multiprocessors," in Proc. ISCAS'88, May 1988, pp. 811-814.
13. D. Lilja, "The impact of parallel loop scheduling strategies on prefetching in a shared memory multi-processor," IEEE Trans. Parallel Distrib. Syst., vol. 5, pp. 573-584, June 1994.
14. T. Fujii and N. Ohta, "A load balancing technique for video signal processing on a multicomputer type DSP," in Proc. ICASSP'88, 1988, pp. 1981-1984.
15. M. Engels, R. Lauwereins, J. Peperstraete, and A. Van Roermond, "Design of a processor board for a programmable multi-VSP system," J. VLSI Signal Processing (Special Issue on Video/Image Signal Processing), vol. 5, pp. 171-184, Apr. 1993.
16. M. Schwiegershausen, M. Schönfeld, and P. Pirsch, "Mapping complex image processing algorithms onto heterogeneous multiprocessors regarding architecture dependent performance parameters," in Proc. Int. Workshop Algorithms and Parallel VLSI Architectures, Leuven, Belgium, Aug. 1994. Also in Algorithms and Parallel VLSI Architectures III, M. Moonen and F. Catthoor, Eds. Amsterdam: Elsevier, 1995.
17. L. De Vos and M. Stegherr, "Parameterizable VLSI architectures for the full-search block-matching algorithm," IEEE Trans. Circuits Syst., vol. 36, pp. 1309-1316, Oct. 1989.
18. Y. Jehng, L. Chen, and T. Chiueh, "An efficient and simple VLSI tree architecture for motion estimation algorithms," IEEE Trans. Signal Processing, vol. 41, pp. 889-900, Feb. 1993.
19. T. Komarek and P. Pirsch, "Array architectures for block matching algorithms," IEEE Trans. Circuits Syst., vol. 36, Oct. 1989.
20. J. Rosseel, F. Catthoor, and H. De Man, "The systematic design of a motion estimation array architecture," in Proc. IEEE Int. Conf. Application Specific Array Processors. IEEE Computer Society Press, 1991, pp. 40-54.
21. T. Akiyama, H. Aono, K. Aoki, K. Ler, B. Wilson, T. Araki, T. Morishige, H. Takeno, A. Sato, S. Nakatani, and T. Senoh, "MPEG2 video codec using image compression DSP," IEEE Trans. Consumer Electron., vol. 40, pp. 466-472, Aug. 1994.
22. E. De Greef, F. Catthoor, and H. De Man, "A memory-efficient, programmable multi-processor architecture for real-time motion estimation type algorithms," in Proc. Int. Workshop Algorithms and Parallel VLSI Architectures, Aug. 1994. Also in Algorithms and Parallel VLSI Architectures III, M. Moonen and F. Catthoor, Eds. Amsterdam: Elsevier, 1995.
23. M. van Swaaij, F. Franssen, F. Catthoor, and H. De Man, "Automating high-level control flow transformations for DSP memory management," in IEEE Workshop VLSI Signal Processing, Napa Valley, CA, Oct. 1992. Also in VLSI Signal Processing V, K. Yao, R. Jain, and W. Przytula, Eds. New York: IEEE Press, 1992, pp. 397-406.
24. S. Wuytack, F. Catthoor, F. Franssen, L. Nachtergaele, and H. De Man, "Global communication and memory optimizing transformations for low power systems," in Int. Workshop on Low Power, Apr. 1994.
25. D. Le Gall, "MPEG: A video compression standard for multimedia applications," Commun. ACM, vol. 34, pp. 46-58, Apr. 1991.
26. E. De Greef, "Storage size reduction for multimedia applications," Ph.D. dissertation, K. U. Leuven, Belgium, Jan. 1998.
27. D. A. Padua and M. J. Wolfe, "Advanced compiler optimizations for supercomputers, Commun. ACM (Special Issue), vol. 29, no. 12, pp. 1184-1201, 1986.
28. M. E. Wolf and M. S. Lam, "A loop transformation theory and an algorithm to maximize parallelism," IEEE Trans. Parallel Distrib. Syst., vol. 2, pp. 452-471, Oct. 1991.
29. T. H. Meng, B. Gordon, E. Tsern, and A. Hung, "Portable video-on-demand in wireless communication," in Proc. IEEE (Special Issue on Low Power Electronics), vol. 83, pp. 659-680, Apr. 1995.
30. R. Gonzalez and M. Horowitz, "Energy dissipation in general-purpose microprocessors," IEEE J. Solid-State Circuits, vol. 31, pp. 1277-1283, Sept. 1996.
31. P. Landman, "Low power architectural design methodologies," Ph.D. dissertation, University of California, Berkeley, Berkeley, CA 1994.
32. K. Danckaert, F. Catthoor, and H. De Man, "System-level memory management for weakly parallel image processing," in Proc. Euro-Par'96, Lyon, France, Aug. 1996.
33. C. Kulkarni, F. Catthoor, and H. De Man, "Cache optimization for multimedia compilation on embedded processors for low power," in Proc. Int. Parallel Processing Symp., Orlando, FL, Apr. 1998, to be published.
34. S. Wuytack, F. Catthoor, L. Nachtergaele, and H. De Man, "Power exploration for data dominated video applications," in Proc. Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug. 1996.