Instruction scheduling for power reduction in processor-based system design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 855-860

  Tomiyama, Hiroyuki ^a   Ishihara, Tohru ^a   Inoue, Akihiko ^a   Yasuura, Hiroto ^a  

^a KYUSHU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INSTRUCTION CACHE MISS; INSTRUCTION SCHEDULING; MAIN MEMORY; ON-CHIP CACHE; POWER CONSUMED; POWER REDUCTIONS; SCHEDULING PROBLEM; SWITCHING ACTIVITIES;

EID: 20444438621     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655958     Document Type: Conference Paper

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