The soft error problem: An architectural perspective

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2005, Pages 243-247

  Mukherjee, Shubhendu S ^a   Emer, Joel ^a   Reinhardt, Steven K ^a,b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28444483117     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2005.37     Document Type: Conference Paper

References (20)

1. T.Austin, "DIVA: A Reliable Substrate for Deep Submicron Microarchitccture Design," ACM/IEEE 32nd Annual Symposium on Microarchitecture (MICRO-32), November 1999.
2. Robert Baumann, "Soft Error Rate Overview and Technology Trends," 2002 Reliability Physics Tutorial Notes, Reliability Fundamentals, Sunday, April 7, 2002.
3. D. Bossen, "CMOS Soft Errors and Server Design," 2002 IRPS Tutorial Notes - Reliability Fundamentals," April 7, 2002.
4. T. Calin, et al., "Topology-Related Upset Mechanisms in Design Hardened Storage Cells," Radiation and Its Effects on Components and Systems, 1997. RADECS 97.
5. E.H.Cannon. et al "SRAM SER in 90, 130 and 180 nm Bulk and SOI Technologies," International Reliability Physics Symposium, 2004.
6. S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walstra, and C. Dai, "Impact of CMOS Scaling and SOI on soft error rates of logic processes," VLSI Technology Digest of Technical Papers, 2001.
7. T. Karnik, B. Bloechel, K. Soumyanath, V. De, and S. Borkar "Scaling trends of Cosmic Rays induced Soft Errors in static latches beyond 0.18μ," Symposium on VLSI Circuits Digest of Technical Papers, 2001.
8. S. S. Mukherjee, T. Fossum, J. Emer, and S. K. Reinhardt, "Cache Scrubbing in Microprocessors: Myth or Necessity?" 10th International Symposium on Pacific Rim Dependable Computing (PRDC), Papeete, Tahiti, March 2004.
9. S. S. Mukheriee, M. Kontz, and S. K. Reinhardt, "Detailed Design and Evaluation of Redundant Multithreading Alternatives," 29th Annual International Symposium on Computer Architecture (ISCA), 2002.
10. S. S. Mukherjee, C. T. Weaver, J. Emer, S. K. Reinhardt, and T. Auslin, "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor," 36th Annual International Symposium on Microarchitecture (MICRO), December 2003
11. E. Normand, "Single Event Upset at Ground Level," IEEE Transactions on Nuclear Science, Vol. 43, No. 6, Dec. 1996.
12. S. K. Reinhardt and S. S. Mukherjee, "Transient Fault Detection via Simultaneous Multithreading," 27th Annual International Symposium on Computer Architecture (ISCA), June 2000.
13. N. Seifert and N. Tam, "Timing Vulnerability Factor of Sequentials," IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 3, Sep. 2004.
14. P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, and L.Alvisi, "Modeling the Effect of Technology Trends on the Soft Error Rate of Combinatorial Logic," Dependable Systems and Networks (DSN), 2002.
15. T.J. Siegel, et al., "IBM's S/390 05 Microprocessor Design," IEEE Micro, pp 12-23, Mach/April 1999.
16. J. C. Smolens, B.T. Gold, J. Kim, B. Falsafi, J. C. Hoe, and A. G. Nowatzyk, "Fingerprinting: Bounding Soft Error Detection Latency and Bandwidth," Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2004.
17. Tosaka, et al., "Impact of Cosmic Ray Neutron Induced Soft Errors, on Advanced Submicron CMOS circuits," Symposium on VLSI Technology Digest of Technical papers, 1996.
18. N. Wang, M. Fertig, and S. Paid, "Y-Branches: When You Come to a Fork in the Road, Take It," 12th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2003.
19. N. Wang, J. Quek, T. M. Rafacz, and S. Patel, "Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline," International Conference on Dependable Systems and Networks, June 2004.
20. C.Weaver, J. Emer, S.S. Mukherjee, and S.K.Reinhardt, "Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor," 31st Annual International Symposium on Computer Architecture (ISCA), 2004.