메뉴 건너뛰기




Volumn 52, Issue 11, 2005, Pages 2455-2462

Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs

Author keywords

FinFET; Implant to silicide (ITS); Schottky barrier (SB); Silicon on insulator (SOI)

Indexed keywords

ANNEALING; CRYSTAL MICROSTRUCTURE; CURRENT VOLTAGE CHARACTERISTICS; ELECTRON DIFFRACTION; GRAIN SIZE AND SHAPE; LEAKAGE CURRENTS; SCHOTTKY BARRIER DIODES; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; THERMAL EFFECTS; THERMODYNAMIC STABILITY; TRANSMISSION ELECTRON MICROSCOPY;

EID: 27744473956     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.857178     Document Type: Article
Times cited : (25)

References (25)
  • 1
    • 84939180950 scopus 로고
    • "SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain"
    • Nov.
    • T. Lepselter and S. M. Sze, "SB-IGFET: an insulated-gate field-effect transistor using Schottky barrier contacts for source and drain," Proc. IEEE, no. 11, pp. 1400-1401, Nov. 1968.
    • (1968) Proc. IEEE , Issue.11 , pp. 1400-1401
    • Lepselter, T.1    Sze, S.M.2
  • 4
    • 36449006867 scopus 로고
    • "Silicon field-effect transistor based on quantum tunneling"
    • J. R. Tucker, C. Wang, and P. Scott Carney, "Silicon field-effect transistor based on quantum tunneling," Appl. Phys. Lett., vol. 65, pp. 618-620, 1994.
    • (1994) Appl. Phys. Lett. , vol.65 , pp. 618-620
    • Tucker, J.R.1    Wang, C.2    Scott Carney, P.3
  • 5
    • 0041526001 scopus 로고    scopus 로고
    • "Analysis of the potential distribution in the channel region of a platinum silicided source/drain metal oxide semiconductor field effect transistor"
    • J. P. Snyder, C. R. Helms, and Y. Nishi, "Analysis of the potential distribution in the channel region of a platinum silicided source/drain metal oxide semiconductor field effect transistor," Appl. Phys. Lett., vol. 74, pp. 3407-3409, 1999.
    • (1999) Appl. Phys. Lett. , vol.74 , pp. 3407-3409
    • Snyder, J.P.1    Helms, C.R.2    Nishi, Y.3
  • 6
    • 0024662760 scopus 로고
    • "A novel process for high performance Schottky barrier PMOS"
    • B. Y. Tsui and M. C. Chen, "A novel process for high performance Schottky barrier PMOS," J. Electrochem. Soc., vol. 136, no. 5, pp. 1456-1459, 1989.
    • (1989) J. Electrochem. Soc. , vol.136 , Issue.5 , pp. 1456-1459
    • Tsui, B.Y.1    Chen, M.C.2
  • 7
    • 0030688182 scopus 로고    scopus 로고
    • "Schottky barrier MOSFETs for silicon nanoelectronics"
    • J. R. Tucker, "Schottky barrier MOSFETs for silicon nanoelectronics," in IEEE Proc. Workshop Frontiers Electronics, 1997, pp. 97-100.
    • (1997) IEEE Proc. Workshop Frontiers Electronics , pp. 97-100
    • Tucker, J.R.1
  • 8
    • 0034453418 scopus 로고    scopus 로고
    • "Complementary silicide source/drain thin-body MOSFETs for the 20-nm gate length regime"
    • J. Kedzierski, P. Xuan, E. H. Anderson, J. Boker, T. J. King, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20-nm gate length regime," in IEDM Tech. Dig., 2000, pp. 57-60.
    • (2000) IEDM Tech. Dig. , pp. 57-60
    • Kedzierski, J.1    Xuan, P.2    Anderson, E.H.3    Boker, J.4    King, T.J.5    Hu, C.6
  • 9
    • 0032319113 scopus 로고    scopus 로고
    • "Pt-Si source and drain SOI-MOSFET operating in bi-channel mode"
    • M. Nishisaka, Y. Ochiai, and T. Asano, "Pt-Si source and drain SOI-MOSFET operating in bi-channel mode," in Proc. Device Res. Conf., 1998, pp. 74-75.
    • (1998) Proc. Device Res. Conf. , pp. 74-75
    • Nishisaka, M.1    Ochiai, Y.2    Asano, T.3
  • 10
    • 0038483204 scopus 로고    scopus 로고
    • "Effects of sub-gate bias on the operation of Schottky-barrier SOI MOSFETs having nanoscale channel"
    • Aug.
    • H. C. Lin, M. F. Wang, F. J. Ho, J. T. Liu, Y. Li, T. Y. Huang, and S. M. Sze, "Effects of sub-gate bias on the operation of Schottky-barrier SOI MOSFETs having nanoscale channel," in Proc. IEEE Conf. Nanotechnology, Aug. 2002, pp. 205-208.
    • (2002) Proc. IEEE Conf. Nanotechnology , pp. 205-208
    • Lin, H.C.1    Wang, M.F.2    Ho, F.J.3    Liu, J.T.4    Li, Y.5    Huang, T.Y.6    Sze, S.M.7
  • 11
    • 0037672096 scopus 로고    scopus 로고
    • "Schottky source/drain SOI MOSFET with shallow doped extension"
    • M. Nishisaka, S. Matsumoto, and T. Asano, "Schottky source/drain SOI MOSFET with shallow doped extension," Jpn. J. Appl. Phys., vol. 42, pp. 2009-2013, 2003.
    • (2003) Jpn. J. Appl. Phys. , vol.42 , pp. 2009-2013
    • Nishisaka, M.1    Matsumoto, S.2    Asano, T.3
  • 12
    • 2942750455 scopus 로고    scopus 로고
    • "A novel 25 nm modified-Schottky-barrier FinFET with high performance"
    • B. Y. Tsui and C. P. Lin, "A novel 25 nm modified-Schottky-barrier FinFET with high performance," IEEE Electron Device Lett., vol. 25, no. 6, pp. 430-432, 2004.
    • (2004) IEEE Electron Device Lett. , vol.25 , Issue.6 , pp. 430-432
    • Tsui, B.Y.1    Lin, C.P.2
  • 13
    • 84907707336 scopus 로고    scopus 로고
    • "Corner effect in double and triple gate Fin-FETs"
    • Burenkov and J. Lorenz, "Corner effect in double and triple gate Fin-FETs" in European Solid-State Device Research, 2003, pp. 135-138.
    • (2003) European Solid-State Device Research , pp. 135-138
    • Burenkov1    Lorenz, J.2
  • 15
    • 3743129734 scopus 로고
    • + implantation and low temperature annealing"
    • + implantation and low temperature annealing," J. Appl. Phys., vol. 69, pp. 4354-4363, 1991.
    • (1991) J. Appl. Phys. , vol.69 , pp. 4354-4363
    • Tsui, B.Y.1    Tsai, J.Y.2    Chen, M.C.3
  • 16
    • 0030080749 scopus 로고    scopus 로고
    • "Formation of cobalt silicided shallow junction using implant into/ through silicide technology and low temperature furnace annealing"
    • Feb.
    • B. S. Chen and M. C. Chen, "Formation of cobalt silicided shallow junction using implant into/through silicide technology and low temperature furnace annealing," IEEE Trans. Electron Devices, vol. 43, no. 2, pp. 258-266, Feb. 1996.
    • (1996) IEEE Trans. Electron Devices , vol.43 , Issue.2 , pp. 258-266
    • Chen, B.S.1    Chen, M.C.2
  • 17
    • 0041779946 scopus 로고    scopus 로고
    • "Formation of NiSi-silicide p+n shallow junctions using implant-through-silicide and low-temperature furnace annealing"
    • C. C. Wang, C. J. Lin, and M. C. Chen, "Formation of NiSi-silicide p+n shallow junctions using implant-through-silicide and low-temperature furnace annealing," J. Electrochem. Soc., vol. 150, no. 9, pp. 557-562, 2003.
    • (2003) J. Electrochem. Soc. , vol.150 , Issue.9 , pp. 557-562
    • Wang, C.C.1    Lin, C.J.2    Chen, M.C.3
  • 19
    • 0030214332 scopus 로고    scopus 로고
    • "Epitaxial growth of NiSi2 on (111) Si inside 0.1-0.6 mm oxide openings prepared by electron beam lithography"
    • J. Y. Yew, L. J. Chen, and K. Nakamura, "Epitaxial growth of NiSi2 on (111) Si inside 0.1-0.6 mm oxide openings prepared by electron beam lithography," Appl. Phys. Lett., vol. 69, no. 7, pp. 999-1001, 1996.
    • (1996) Appl. Phys. Lett. , vol.69 , Issue.7 , pp. 999-1001
    • Yew, J.Y.1    Chen, L.J.2    Nakamura, K.3
  • 20
    • 27744472260 scopus 로고    scopus 로고
    • "PN junction surface potential images measured by Kelvin probe force microscopy"
    • P. C. Su, C. M. Hsieh, and B. Y. Tsui, "PN junction surface potential images measured by Kelvin probe force microscopy," WSEAS Trans. Electron., vol. 1, no. 1, pp. 124-127, 2004.
    • (2004) WSEAS Trans. Electron. , vol.1 , Issue.1 , pp. 124-127
    • Su, P.C.1    Hsieh, C.M.2    Tsui, B.Y.3
  • 23
    • 0036684706 scopus 로고    scopus 로고
    • "FinFET design considerations based on 3-D simulation and analytical modeling"
    • Aug.
    • G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E. C. C. Kan, "FinFET design considerations based on 3-D simulation and analytical modeling," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1411-1419, Aug. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.8 , pp. 1411-1419
    • Pei, G.1    Kedzierski, J.2    Oldiges, P.3    Ieong, M.4    Kan, E.C.C.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.