A single-ended disturb-free 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 6, 2012, Pages 1469-1482

  Tu, Ming Hsien ^a   Lin, Jihi Yu ^a,b   Tsai, Ming Chien ^a   Lu, Chien Yu ^a   Lin, Yuh Jiun ^a   Wang, Meng Hsueh ^a,b   Huang, Huan Shun ^a,b   Lee, Kuen Di ^a,b   Shih, Wei Chiang ^a,b   Jou, Shyh Jye ^a   Chuang, Ching Te ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b FARADAY TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

Low power; low voltage; negative bit line (BL); subthreshold SRAM cell; timing tracing

Indexed keywords

BIT LINES; LOW POWER; LOW VOLTAGES; SUB-THRESHOLD SRAM; TIMING TRACING;

CMOS INTEGRATED CIRCUITS; STATIC RANDOM ACCESS STORAGE;

TIMING CIRCUITS;

EID: 84861719440     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2187474     Document Type: Article

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