Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems

ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 164-167

  Tajalli, Armin ^a   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; CMOS CIRCUITS; DIGITAL SYSTEM; MEMORY CELL; NANOMETER CMOS; POWER CONSUMPTION; POWER EFFICIENCY; SOURCE COUPLED LOGIC; STATIC RANDOM ACCESS MEMORY; SUB-THRESHOLD LEAKAGE; SUBTHRESHOLD SCL; ULTRA-LOW POWER;

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; STATIC RANDOM ACCESS STORAGE; TOPOLOGY;

COUPLED CIRCUITS;

EID: 72849147344     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2009.5325939     Document Type: Conference Paper

References (10)

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