A read-disturb-free, differential sensing 1R/1W Port, 8T bitcell array

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 9, 2011, Pages 1727-1730

  Kulkarni, Jaydeep P ^a   Goel, Ashish ^b   Ndai, Patrick ^b   Roy, Kaushik ^b  

^a INTEL CORPORATION   (United States)

^b Purdue University   (United States)

Author keywords

1R 1W port SRAM; 8 transistor (8T) bitcell; Differential sensing; low voltage static random access memory (SRAM); process tolerance

Indexed keywords

1R/1W PORT SRAM; BITCELL; DIFFERENTIAL SENSING; LOW VOLTAGES; PROCESS TOLERANCE;

CMOS INTEGRATED CIRCUITS; TRANSISTORS;

STATIC RANDOM ACCESS STORAGE;

EID: 79960984427     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2055169     Document Type: Article

References (11)

1. K. Zhang, F. Hamzaoglu, and Y. Wang, "Low power SRAM in nanoscale CMOS technologies," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 145-151, Jan. 2008.
2. N.Verma and A. P. Chandrakasan, Ultra Low Voltage SRAM Design. New York: Springer, 2010, pp. 89-126.
3. A. Bhavnagarwala, X. Tang, and J. Meindl, "The impact of intrinsic device fluctuations on CMOSSRAMcell stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001. (Pubitemid 32407171)
4. M. M. Khellah, A. Keshavarzi, D. Somasekhar, T. Karnik, and V. De, "Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell," in Proc. Int. Conf. Integr. Circuit Des. Technol., Jun. 2008, pp. 185-189.
5. L. Chang, D. Fried, J. Hergenrother, J. Sleight, R. Dennard, R. R. Montoye, L. Sekaric, S. McNab, W. Topol, C. Adams, K. Guarini, and W. Haensch, "Stable SRAM cell design for the 32 nm node and beyond," in Proc. Symp. VLSI Technol., 2005, pp. 128-129. (Pubitemid 43897595)
6. Z. Liu and V. Kursun, "High read stability and low leakage cache memory cell," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 4, pp. 488-492, Apr. 2008.
7. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 12, pp. 1859-1880, Dec. 2005.
8. F. Arnaud et al., "A functional 0.69 m embedded 6T-SRAM bit cell for 65 nm CMOS platform," in Proc. VLSI Technol. Symp., 2003, pp. 65-66.
9. A. Meixner and J. Banik, "Weak write test mode: An SRAM cell stability design for test technique," in Proc. Int. Test Conf., Nov. 1997, pp. 1043-1052.
10. K. Agarwal and S. Nassif, "Statistical analysis of SRAM cell stability," in Proc. Des. Autom. Conf., 2006, pp. 57-62. (Pubitemid 47113867)
11. S. Mukhopadhyay, K. Kim, H. Mahmoodi, and K. Roy, "Design of a process variation tolerant self-repairing SRAM for yield enhancement in nano scaled CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1370-1382, Jun. 2007. (Pubitemid 46853245)