Novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2000, Pages

  Wang, B T ^a   Kuo, James B ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN; VLSI CIRCUITS;

SINGLE BIT LINE SIMULTANEOUS READ AND WRITE ACCESS (SBLSRWA); STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0033681467     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.857606     Document Type: Conference Paper

References (3)