SRAM write-ability improvement with transient negative bit-line voltage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 1, 2011, Pages 24-32

  Mukhopadhyay, Saibal ^a   Rao, Rahul M ^b   Kim, Jae Joon ^b   Chuang, Ching Te ^c  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Capacitive coupling; SRAM; variation; write ability

Indexed keywords

BIT LINES; CAPACITIVE COUPLINGS; CMOS TECHNOLOGY; DEVICE PARAMETERS; FAILURE PROBABILITY; NEGATIVE VOLTAGE; OFF-CHIP; ON CHIPS; SRAM; SRAM CELL; STATISTICAL SIMULATION; SUB-100 NM; VARIATION; WRITE OPERATIONS; WRITE-ABILITY;

CMOS INTEGRATED CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 78650864443     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2029114     Document Type: Article

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