Ultralow-voltage process-variation-tolerant schmitt-trigger-based SRAM design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 2, 2012, Pages 319-332

  Kulkarni, Jaydeep P ^a   Roy, Kaushik ^b  

^a INTEL CORPORATION   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Low voltage SRAM; process tolerance; Schmitt Trigger (ST); V min

Indexed keywords

BITCELL; CMOS TECHNOLOGY; DESIGN REQUIREMENTS; FEEDBACK MECHANISMS; MEASUREMENT RESULTS; PROCESS TOLERANCE; PROCESS VARIATION; SCHMITT-TRIGGER (ST); SRAM DESIGN; STATIC NOISE MARGIN; STATIC RANDOM ACCESS MEMORY; SUPPLY VOLTAGES; TECHNOLOGY NODES; ULTRA-LOW-VOLTAGE; WRITE OPERATIONS;

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 84856277403     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2100834     Document Type: Article

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