Fundamental data retention limits in sram standby - Experimental results

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 92-97

  Kumar, Animesh ^a   Qin, Huifang ^a   Ishwar, Prakash ^b   Rabaey, Jan ^a   Ramchandran, Kannan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b BOSTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL RESULTS; CMOS PROCESSING; CYCLE APPLICATIONS; DATA-RETENTION; DEEP-SUB MICRON; ELECTRONIC DESIGNS; FUNDAMENTAL LIMITS; HAMMING CODES; INTERNATIONAL SYMPOSIUM; INTRA-CHIP VARIATION; LEAKAGE POWER; LEAKAGE POWER REDUCTION; MINIMIZATION OF POWER; SENSOR NODES; SRAM CELLS; SUPPLY VOLTAGES; TOTAL POWER;

CMOS INTEGRATED CIRCUITS; ELECTRONICS ENGINEERING; ERROR CORRECTION; STATIC RANDOM ACCESS STORAGE; TELECOMMUNICATION EQUIPMENT;

DATA REDUCTION;

EID: 49749109542     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479705     Document Type: Conference Paper

References (6)

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